diff options
| author | Tony Luck <tony.luck@intel.com> | 2005-10-31 10:51:57 -0800 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-10-31 10:51:57 -0800 |
| commit | c7fb577e2a6cb04732541f2dc402bd46747f7558 (patch) | |
| tree | df3b1a1922ed13bfbcc45d08650c38beeb1a7bd1 /include/asm-mips/war.h | |
| parent | 9cec58dc138d6fcad9f447a19c8ff69f6540e667 (diff) | |
| parent | 581c1b14394aee60aff46ea67d05483261ed6527 (diff) | |
manual update from upstream:
Applied Al's change 06a544971fad0992fe8b92c5647538d573089dd4
to new location of swiotlb.c
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2..ad374bd3f13 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif |