Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (49 commits)
  MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq
  MIPS: Move ptrace prototypes to ptrace.h
  MIPS: Ptrace support for HARDWARE_WATCHPOINTS
  MIPS: Scheduler support for HARDWARE_WATCHPOINTS.
  MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
  MIPS: Probe watch registers and report configuration.
  MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
  MIPS: Add HARDWARE_WATCHPOINTS configure option.
  MIPS: Replace use of <asm-generic/uaccess.h> with native implementations.
  MIPS: TXx9: Add TX4939 ATA support (v2)
  MIPS: Rewrite spinlocks to ticket locks.
  MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.
  MIPS: IP checksums: Remove unncessary .set pseudos
  MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.
  MIPS: Move headfiles to new location below arch/mips/include
  MIPS: Alchemy: rename directory
  MIPS: Optimize get_user and put_user for 64-bit
  MIPS: TXx9: Implement prom_free_prom_memory
  MIPS: TXx9: Add RBTX4939 board support
  MIPS: TXx9: Add TX4939 SoC support
  ...

14 files changed, 0 insertions, 1547 deletions

diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
deleted file mode 100644
index f3bc7efa260..00000000000
--- a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  IDT RC32434 specific CPU feature overrides
- *
- *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This file was derived from: include/asm-mips/cpu-features.h
- *	Copyright (C) 2003, 2004 Ralf Baechle
- *	Copyright (C) 2004 Maciej W. Rozycki
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version 2
- *  of the License, or (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the
- *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- *  Boston, MA  02110-1301, USA.
- */
-#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
-
-/*
- * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
- */
-#define cpu_has_tlb			1
-#define cpu_has_4kex			1
-#define cpu_has_3k_cache		0
-#define cpu_has_4k_cache		1
-#define cpu_has_tx39_cache		0
-#define cpu_has_sb1_cache		0
-#define cpu_has_fpu			0
-#define cpu_has_32fpr			0
-#define cpu_has_counter			1
-#define cpu_has_watch			1
-#define cpu_has_divec			1
-#define cpu_has_vce			0
-#define cpu_has_cache_cdex_p		0
-#define cpu_has_cache_cdex_s		0
-#define cpu_has_prefetch		1
-#define cpu_has_mcheck			1
-#define cpu_has_ejtag			1
-#define cpu_has_llsc			1
-
-#define cpu_has_mips16			0
-#define cpu_has_mdmx			0
-#define cpu_has_mips3d			0
-#define cpu_has_smartmips		0
-
-#define cpu_has_vtag_icache		0
-/* #define cpu_has_dc_aliases		? */
-/* #define cpu_has_ic_fills_f_dc	? */
-/* #define cpu_has_pindexed_dcache	? */
-
-/* #define cpu_icache_snoops_remote_store	? */
-
-#define cpu_has_mips32r1		1
-#define cpu_has_mips32r2		0
-#define cpu_has_mips64r1		0
-#define cpu_has_mips64r2		0
-
-#define cpu_has_dsp			0
-#define cpu_has_mipsmt			0
-
-/* #define cpu_has_nofpuex		? */
-#define cpu_has_64bits			0
-#define cpu_has_64bit_zero_reg		0
-#define cpu_has_64bit_gp_regs		0
-#define cpu_has_64bit_addresses		0
-
-#define cpu_has_inclusive_pcaches	0
-
-#define cpu_dcache_line_size()		16
-#define cpu_icache_line_size()		16
-
-#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h
deleted file mode 100644
index 291e2cf9dde..00000000000
--- a/include/asm-mips/mach-rc32434/ddr.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- *  Definitions for the DDR registers
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef _ASM_RC32434_DDR_H_
-#define _ASM_RC32434_DDR_H_
-
-#include <asm/mach-rc32434/rb.h>
-
-/* DDR register structure */
-struct ddr_ram {
-	u32 ddrbase;
-	u32 ddrmask;
-	u32 res1;
-	u32 res2;
-	u32 ddrc;
-	u32 ddrabase;
-	u32 ddramask;
-	u32 ddramap;
-	u32 ddrcust;
-	u32 ddrrdc;
-	u32 ddrspare;
-};
-
-#define DDR0_PHYS_ADDR		0x18018000
-
-/* DDR banks masks */
-#define DDR_MASK		0xffff0000
-#define DDR0_BASE_MSK		DDR_MASK
-#define DDR1_BASE_MSK		DDR_MASK
-
-/* DDR bank0 registers */
-#define RC32434_DDR0_ATA_BIT		5
-#define RC32434_DDR0_ATA_MSK		0x000000E0
-#define RC32434_DDR0_DBW_BIT		8
-#define RC32434_DDR0_DBW_MSK		0x00000100
-#define RC32434_DDR0_WR_BIT		9
-#define RC32434_DDR0_WR_MSK		0x00000600
-#define RC32434_DDR0_PS_BIT		11
-#define RC32434_DDR0_PS_MSK		0x00001800
-#define RC32434_DDR0_DTYPE_BIT		13
-#define RC32434_DDR0_DTYPE_MSK		0x0000e000
-#define RC32434_DDR0_RFC_BIT		16
-#define RC32434_DDR0_RFC_MSK		0x000f0000
-#define RC32434_DDR0_RP_BIT		20
-#define RC32434_DDR0_RP_MSK		0x00300000
-#define RC32434_DDR0_AP_BIT		22
-#define RC32434_DDR0_AP_MSK		0x00400000
-#define RC32434_DDR0_RCD_BIT		23
-#define RC32434_DDR0_RCD_MSK		0x01800000
-#define RC32434_DDR0_CL_BIT		25
-#define RC32434_DDR0_CL_MSK		0x06000000
-#define RC32434_DDR0_DBM_BIT		27
-#define RC32434_DDR0_DBM_MSK		0x08000000
-#define RC32434_DDR0_SDS_BIT		28
-#define RC32434_DDR0_SDS_MSK		0x10000000
-#define RC32434_DDR0_ATP_BIT		29
-#define RC32434_DDR0_ATP_MSK		0x60000000
-#define RC32434_DDR0_RE_BIT		31
-#define RC32434_DDR0_RE_MSK		0x80000000
-
-/* DDR bank C registers */
-#define RC32434_DDRC_MSK(x)		BIT_TO_MASK(x)
-#define RC32434_DDRC_CES_BIT		0
-#define RC32434_DDRC_ACE_BIT		1
-
-/* Custom DDR bank registers */
-#define RC32434_DCST_MSK(x)		BIT_TO_MASK(x)
-#define RC32434_DCST_CS_BIT		0
-#define RC32434_DCST_CS_MSK		0x00000003
-#define RC32434_DCST_WE_BIT		2
-#define RC32434_DCST_RAS_BIT		3
-#define RC32434_DCST_CAS_BIT		4
-#define RC32434_DSCT_CKE_BIT		5
-#define RC32434_DSCT_BA_BIT		6
-#define RC32434_DSCT_BA_MSK		0x000000c0
-
-/* DDR QSC registers */
-#define RC32434_QSC_DM_BIT		0
-#define RC32434_QSC_DM_MSK		0x00000003
-#define RC32434_QSC_DQSBS_BIT		2
-#define RC32434_QSC_DQSBS_MSK		0x000000fc
-#define RC32434_QSC_DB_BIT		8
-#define RC32434_QSC_DB_MSK		0x00000100
-#define RC32434_QSC_DBSP_BIT		9
-#define RC32434_QSC_DBSP_MSK		0x01fffe00
-#define RC32434_QSC_BDP_BIT		25
-#define RC32434_QSC_BDP_MSK		0x7e000000
-
-/* DDR LLC registers */
-#define RC32434_LLC_EAO_BIT		0
-#define RC32434_LLC_EAO_MSK		0x00000001
-#define RC32434_LLC_EO_BIT		1
-#define RC32434_LLC_EO_MSK		0x0000003e
-#define RC32434_LLC_FS_BIT		6
-#define RC32434_LLC_FS_MSK		0x000000c0
-#define RC32434_LLC_AS_BIT		8
-#define RC32434_LLC_AS_MSK		0x00000700
-#define RC32434_LLC_SP_BIT		11
-#define RC32434_LLC_SP_MSK		0x001ff800
-
-/* DDR LLFC registers */
-#define RC32434_LLFC_MSK(x)		BIT_TO_MASK(x)
-#define RC32434_LLFC_MEN_BIT		0
-#define RC32434_LLFC_EAN_BIT		1
-#define RC32434_LLFC_FF_BIT		2
-
-/* DDR DLLTA registers */
-#define RC32434_DLLTA_ADDR_BIT		2
-#define RC32434_DLLTA_ADDR_MSK		0xfffffffc
-
-/* DDR DLLED registers */
-#define RC32434_DLLED_MSK(x)		BIT_TO_MASK(x)
-#define RC32434_DLLED_DBE_BIT		0
-#define RC32434_DLLED_DTE_BIT		1
-
-#endif  /* _ASM_RC32434_DDR_H_ */
diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h
deleted file mode 100644
index 5f898b5873f..00000000000
--- a/include/asm-mips/mach-rc32434/dma.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *		All rights reserved.
- *
- * DMA register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- */
-
-#ifndef __ASM_RC32434_DMA_H
-#define __ASM_RC32434_DMA_H
-
-#include <asm/mach-rc32434/rb.h>
-
-#define DMA0_BASE_ADDR			0x18040000
-
-/*
- * DMA descriptor (in physical memory).
- */
-
-struct dma_desc {
-	u32 control;			/* Control. use DMAD_* */
-	u32 ca;				/* Current Address. */
-	u32 devcs;			/* Device control and status. */
-	u32 link;			/* Next descriptor in chain. */
-};
-
-#define DMA_DESC_SIZ			sizeof(struct dma_desc)
-#define DMA_DESC_COUNT_BIT		0
-#define DMA_DESC_COUNT_MSK		0x0003ffff
-#define DMA_DESC_DS_BIT			20
-#define DMA_DESC_DS_MSK			0x00300000
-
-#define DMA_DESC_DEV_CMD_BIT		22
-#define DMA_DESC_DEV_CMD_MSK		0x01c00000
-
-/* DMA command sizes */
-#define DMA_DESC_DEV_CMD_BYTE		0
-#define DMA_DESC_DEV_CMD_HLF_WD		1
-#define DMA_DESC_DEV_CMD_WORD		2
-#define DMA_DESC_DEV_CMD_2WORDS		3
-#define DMA_DESC_DEV_CMD_4WORDS		4
-#define DMA_DESC_DEV_CMD_6WORDS		5
-#define DMA_DESC_DEV_CMD_8WORDS		6
-#define DMA_DESC_DEV_CMD_16WORDS	7
-
-/* DMA descriptors interrupts */
-#define DMA_DESC_COF			(1 << 25) /* Chain on finished */
-#define DMA_DESC_COD			(1 << 26) /* Chain on done */
-#define DMA_DESC_IOF			(1 << 27) /* Interrupt on finished */
-#define DMA_DESC_IOD			(1 << 28) /* Interrupt on done */
-#define DMA_DESC_TERM			(1 << 29) /* Terminated */
-#define DMA_DESC_DONE			(1 << 30) /* Done */
-#define DMA_DESC_FINI			(1 << 31) /* Finished */
-
-/*
- * DMA register (within Internal Register Map).
- */
-
-struct dma_reg {
-	u32 dmac;		/* Control. */
-	u32 dmas;		/* Status. */
-	u32 dmasm;		/* Mask. */
-	u32 dmadptr;		/* Descriptor pointer. */
-	u32 dmandptr;		/* Next descriptor pointer. */
-};
-
-/* DMA channels specific registers */
-#define DMA_CHAN_RUN_BIT		(1 << 0)
-#define DMA_CHAN_DONE_BIT		(1 << 1)
-#define DMA_CHAN_MODE_BIT		(1 << 2)
-#define DMA_CHAN_MODE_MSK		0x0000000c
-#define  DMA_CHAN_MODE_AUTO		0
-#define  DMA_CHAN_MODE_BURST		1
-#define  DMA_CHAN_MODE_XFRT		2
-#define  DMA_CHAN_MODE_RSVD		3
-#define DMA_CHAN_ACT_BIT		(1 << 4)
-
-/* DMA status registers */
-#define DMA_STAT_FINI			(1 << 0)
-#define DMA_STAT_DONE			(1 << 1)
-#define DMA_STAT_CHAIN			(1 << 2)
-#define DMA_STAT_ERR			(1 << 3)
-#define DMA_STAT_HALT			(1 << 4)
-
-/*
- * DMA channel definitions
- */
-
-#define DMA_CHAN_ETH_RCV		0
-#define DMA_CHAN_ETH_XMT		1
-#define DMA_CHAN_MEM_TO_FIFO		2
-#define DMA_CHAN_FIFO_TO_MEM		3
-#define DMA_CHAN_PCI_TO_MEM		4
-#define DMA_CHAN_MEM_TO_PCI		5
-#define DMA_CHAN_COUNT			6
-
-struct dma_channel {
-	struct dma_reg ch[DMA_CHAN_COUNT];
-};
-
-#endif  /* __ASM_RC32434_DMA_H */
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h
deleted file mode 100644
index 173a9f9146c..00000000000
--- a/include/asm-mips/mach-rc32434/dma_v.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *		All rights reserved.
- *
- * DMA register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- */
-
-#ifndef _ASM_RC32434_DMA_V_H_
-#define _ASM_RC32434_DMA_V_H_
-
-#include  <asm/mach-rc32434/dma.h>
-#include  <asm/mach-rc32434/rc32434.h>
-
-#define DMA_CHAN_OFFSET		0x14
-#define IS_DMA_USED(X)		(((X) & \
-				(DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
-				!= 0)
-#define DMA_COUNT(count)	((count) & DMA_DESC_COUNT_MSK)
-
-#define DMA_HALT_TIMEOUT	500
-
-static inline int rc32434_halt_dma(struct dma_reg *ch)
-{
-	int timeout = 1;
-	if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
-		__raw_writel(0, &ch->dmac);
-		for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-			if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
-				__raw_writel(0, &ch->dmas);
-				break;
-			}
-		}
-	}
-
-	return timeout ? 0 : 1;
-}
-
-static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
-{
-	__raw_writel(0, &ch->dmandptr);
-	__raw_writel(dma_addr, &ch->dmadptr);
-}
-
-static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
-{
-	__raw_writel(dma_addr, &ch->dmandptr);
-}
-
-#endif  /* _ASM_RC32434_DMA_V_H_ */
diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h
deleted file mode 100644
index a25cbc56173..00000000000
--- a/include/asm-mips/mach-rc32434/eth.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- *  Definitions for the Ethernet registers
- *
- *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef	__ASM_RC32434_ETH_H
-#define	__ASM_RC32434_ETH_H
-
-
-#define ETH0_BASE_ADDR		0x18060000
-
-struct eth_regs {
-	u32 ethintfc;
-	u32 ethfifott;
-	u32 etharc;
-	u32 ethhash0;
-	u32 ethhash1;
-	u32 ethu0[4];		/* Reserved. */
-	u32 ethpfs;
-	u32 ethmcp;
-	u32 eth_u1[10];		/* Reserved. */
-	u32 ethspare;
-	u32 eth_u2[42];		/* Reserved. */
-	u32 ethsal0;
-	u32 ethsah0;
-	u32 ethsal1;
-	u32 ethsah1;
-	u32 ethsal2;
-	u32 ethsah2;
-	u32 ethsal3;
-	u32 ethsah3;
-	u32 ethrbc;
-	u32 ethrpc;
-	u32 ethrupc;
-	u32 ethrfc;
-	u32 ethtbc;
-	u32 ethgpf;
-	u32 eth_u9[50];		/* Reserved. */
-	u32 ethmac1;
-	u32 ethmac2;
-	u32 ethipgt;
-	u32 ethipgr;
-	u32 ethclrt;
-	u32 ethmaxf;
-	u32 eth_u10;		/* Reserved. */
-	u32 ethmtest;
-	u32 miimcfg;
-	u32 miimcmd;
-	u32 miimaddr;
-	u32 miimwtd;
-	u32 miimrdd;
-	u32 miimind;
-	u32 eth_u11;		/* Reserved. */
-	u32 eth_u12;		/* Reserved. */
-	u32 ethcfsa0;
-	u32 ethcfsa1;
-	u32 ethcfsa2;
-};
-
-/* Ethernet interrupt registers */
-#define ETH_INT_FC_EN		(1 << 0)
-#define ETH_INT_FC_ITS		(1 << 1)
-#define ETH_INT_FC_RIP		(1 << 2)
-#define ETH_INT_FC_JAM		(1 << 3)
-#define ETH_INT_FC_OVR		(1 << 4)
-#define ETH_INT_FC_UND		(1 << 5)
-#define ETH_INT_FC_IOC		0x000000c0
-
-/* Ethernet FIFO registers */
-#define ETH_FIFI_TT_TTH_BIT	0
-#define ETH_FIFO_TT_TTH		0x0000007f
-
-/* Ethernet ARC/multicast registers */
-#define ETH_ARC_PRO		(1 << 0)
-#define ETH_ARC_AM		(1 << 1)
-#define ETH_ARC_AFM		(1 << 2)
-#define ETH_ARC_AB		(1 << 3)
-
-/* Ethernet SAL registers */
-#define ETH_SAL_BYTE_5		0x000000ff
-#define ETH_SAL_BYTE_4		0x0000ff00
-#define ETH_SAL_BYTE_3		0x00ff0000
-#define ETH_SAL_BYTE_2		0xff000000
-
-/* Ethernet SAH registers */
-#define ETH_SAH_BYTE1		0x000000ff
-#define ETH_SAH_BYTE0		0x0000ff00
-
-/* Ethernet GPF register */
-#define ETH_GPF_PTV		0x0000ffff
-
-/* Ethernet PFG register */
-#define ETH_PFS_PFD		(1 << 0)
-
-/* Ethernet CFSA[0-3] registers */
-#define ETH_CFSA0_CFSA4		0x000000ff
-#define ETH_CFSA0_CFSA5		0x0000ff00
-#define ETH_CFSA1_CFSA2		0x000000ff
-#define ETH_CFSA1_CFSA3		0x0000ff00
-#define ETH_CFSA1_CFSA0		0x000000ff
-#define ETH_CFSA1_CFSA1		0x0000ff00
-
-/* Ethernet MAC1 registers */
-#define ETH_MAC1_RE		(1 << 0)
-#define ETH_MAC1_PAF		(1 << 1)
-#define ETH_MAC1_RFC		(1 << 2)
-#define ETH_MAC1_TFC		(1 << 3)
-#define ETH_MAC1_LB		(1 << 4)
-#define ETH_MAC1_MR		(1 << 31)
-
-/* Ethernet MAC2 registers */
-#define ETH_MAC2_FD		(1 << 0)
-#define ETH_MAC2_FLC		(1 << 1)
-#define ETH_MAC2_HFE		(1 << 2)
-#define ETH_MAC2_DC		(1 << 3)
-#define ETH_MAC2_CEN		(1 << 4)
-#define ETH_MAC2_PE		(1 << 5)
-#define ETH_MAC2_VPE		(1 << 6)
-#define ETH_MAC2_APE		(1 << 7)
-#define ETH_MAC2_PPE		(1 << 8)
-#define ETH_MAC2_LPE		(1 << 9)
-#define ETH_MAC2_NB		(1 << 12)
-#define ETH_MAC2_BP		(1 << 13)
-#define ETH_MAC2_ED		(1 << 14)
-
-/* Ethernet IPGT register */
-#define ETH_IPGT		0x0000007f
-
-/* Ethernet IPGR registers */
-#define ETH_IPGR_IPGR2		0x0000007f
-#define ETH_IPGR_IPGR1		0x00007f00
-
-/* Ethernet CLRT registers */
-#define ETH_CLRT_MAX_RET	0x0000000f
-#define ETH_CLRT_COL_WIN	0x00003f00
-
-/* Ethernet MAXF register */
-#define ETH_MAXF		0x0000ffff
-
-/* Ethernet test registers */
-#define ETH_TEST_REG		(1 << 2)
-#define ETH_MCP_DIV		0x000000ff
-
-/* MII registers */
-#define ETH_MII_CFG_RSVD	0x0000000c
-#define ETH_MII_CMD_RD		(1 << 0)
-#define ETH_MII_CMD_SCN		(1 << 1)
-#define ETH_MII_REG_ADDR	0x0000001f
-#define ETH_MII_PHY_ADDR	0x00001f00
-#define ETH_MII_WTD_DATA	0x0000ffff
-#define ETH_MII_RDD_DATA	0x0000ffff
-#define ETH_MII_IND_BSY		(1 << 0)
-#define ETH_MII_IND_SCN		(1 << 1)
-#define ETH_MII_IND_NV		(1 << 2)
-
-/*
- * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
- */
-
-#define ETH_RX_FD		(1 << 0)
-#define ETH_RX_LD		(1 << 1)
-#define ETH_RX_ROK		(1 << 2)
-#define ETH_RX_FM		(1 << 3)
-#define ETH_RX_MP		(1 << 4)
-#define ETH_RX_BP		(1 << 5)
-#define ETH_RX_VLT		(1 << 6)
-#define ETH_RX_CF		(1 << 7)
-#define ETH_RX_OVR		(1 << 8)
-#define ETH_RX_CRC		(1 << 9)
-#define ETH_RX_CV		(1 << 10)
-#define ETH_RX_DB		(1 << 11)
-#define ETH_RX_LE		(1 << 12)
-#define ETH_RX_LOR		(1 << 13)
-#define ETH_RX_CES		(1 << 14)
-#define ETH_RX_LEN_BIT		16
-#define ETH_RX_LEN		0xffff0000
-
-#define ETH_TX_FD		(1 << 0)
-#define ETH_TX_LD		(1 << 1)
-#define ETH_TX_OEN		(1 << 2)
-#define ETH_TX_PEN		(1 << 3)
-#define ETH_TX_CEN		(1 << 4)
-#define ETH_TX_HEN		(1 << 5)
-#define ETH_TX_TOK		(1 << 6)
-#define ETH_TX_MP		(1 << 7)
-#define ETH_TX_BP		(1 << 8)
-#define ETH_TX_UND		(1 << 9)
-#define ETH_TX_OF		(1 << 10)
-#define ETH_TX_ED		(1 << 11)
-#define ETH_TX_EC		(1 << 12)
-#define ETH_TX_LC		(1 << 13)
-#define ETH_TX_TD		(1 << 14)
-#define ETH_TX_CRC		(1 << 15)
-#define ETH_TX_LE		(1 << 16)
-#define ETH_TX_CC		0x001E0000
-
-#endif  /* __ASM_RC32434_ETH_H */
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
deleted file mode 100644
index f946f5f45bb..00000000000
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *	All rights reserved.
- *
- * GPIO register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
- */
-
-#ifndef _RC32434_GPIO_H_
-#define _RC32434_GPIO_H_
-
-#include <linux/types.h>
-
-struct rb532_gpio_reg {
-	u32   gpiofunc;   /* GPIO Function Register
-			   * gpiofunc[x]==0 bit = gpio
-			   * func[x]==1  bit = altfunc
-			   */
-	u32   gpiocfg;	  /* GPIO Configuration Register
-			   * gpiocfg[x]==0 bit = input
-			   * gpiocfg[x]==1 bit = output
-			   */
-	u32   gpiod;	  /* GPIO Data Register
-			   * gpiod[x] read/write gpio pinX status
-			   */
-	u32   gpioilevel; /* GPIO Interrupt Status Register
-			   * interrupt level (see gpioistat)
-			   */
-	u32   gpioistat;  /* Gpio Interrupt Status Register
-			   * istat[x] = (gpiod[x] == level[x])
-			   * cleared in ISR (STICKY bits)
-			   */
-	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
-};
-
-/* UART GPIO signals */
-#define RC32434_UART0_SOUT	(1 << 0)
-#define RC32434_UART0_SIN	(1 << 1)
-#define RC32434_UART0_RTS	(1 << 2)
-#define RC32434_UART0_CTS	(1 << 3)
-
-/* M & P bus GPIO signals */
-#define RC32434_MP_BIT_22	(1 << 4)
-#define RC32434_MP_BIT_23	(1 << 5)
-#define RC32434_MP_BIT_24	(1 << 6)
-#define RC32434_MP_BIT_25	(1 << 7)
-
-/* CPU GPIO signals */
-#define RC32434_CPU_GPIO	(1 << 8)
-
-/* Reserved GPIO signals */
-#define RC32434_AF_SPARE_6	(1 << 9)
-#define RC32434_AF_SPARE_4	(1 << 10)
-#define RC32434_AF_SPARE_3	(1 << 11)
-#define RC32434_AF_SPARE_2	(1 << 12)
-
-/* PCI messaging unit */
-#define RC32434_PCI_MSU_GPIO	(1 << 13)
-
-
-extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
-extern unsigned get_434_reg(unsigned reg_offs);
-extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
-extern unsigned char get_latch_u5(void);
-
-extern int rb532_gpio_get_value(unsigned gpio);
-extern void rb532_gpio_set_value(unsigned gpio, int value);
-extern int rb532_gpio_direction_input(unsigned gpio);
-extern int rb532_gpio_direction_output(unsigned gpio, int value);
-extern void rb532_gpio_set_int_level(unsigned gpio, int value);
-extern int rb532_gpio_get_int_level(unsigned gpio);
-extern void rb532_gpio_set_int_status(unsigned gpio, int value);
-extern int rb532_gpio_get_int_status(unsigned gpio);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	/* Not yet implemented */
-	return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-	/* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-	return rb532_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	return rb532_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return rb532_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-	rb532_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-	return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-	return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h
deleted file mode 100644
index fa65bc3d880..00000000000
--- a/include/asm-mips/mach-rc32434/integ.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *  Definitions for the Watchdog registers
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __RC32434_INTEG_H__
-#define __RC32434_INTEG_H__
-
-#include <asm/mach-rc32434/rb.h>
-
-#define INTEG0_BASE_ADDR	0x18030030
-
-struct integ {
-	u32 errcs;			/* sticky use ERRCS_ */
-	u32 wtcount;			/* Watchdog timer count reg. */
-	u32 wtcompare;			/* Watchdog timer timeout value. */
-	u32 wtc;			/* Watchdog timer control. use WTC_ */
-};
-
-/* Error counters */
-#define RC32434_ERR_WTO		0
-#define RC32434_ERR_WNE		1
-#define RC32434_ERR_UCW		2
-#define RC32434_ERR_UCR		3
-#define RC32434_ERR_UPW		4
-#define RC32434_ERR_UPR		5
-#define RC32434_ERR_UDW		6
-#define RC32434_ERR_UDR		7
-#define RC32434_ERR_SAE		8
-#define RC32434_ERR_WRE		9
-
-/* Watchdog control bits */
-#define RC32434_WTC_EN		0
-#define RC32434_WTC_TO		1
-
-#endif	/* __RC32434_INTEG_H__ */
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
deleted file mode 100644
index cb9e4725f5d..00000000000
--- a/include/asm-mips/mach-rc32434/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_RC32434_IRQ_H
-#define __ASM_RC32434_IRQ_H
-
-#define NR_IRQS	256
-
-#include <asm/mach-generic/irq.h>
-
-#endif  /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
deleted file mode 100644
index 410638f2af7..00000000000
--- a/include/asm-mips/mach-rc32434/pci.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * Initial Release
- */
-
-#ifndef _ASM_RC32434_PCI_H_
-#define _ASM_RC32434_PCI_H_
-
-#define epld_mask ((volatile unsigned char *)0xB900000d)
-
-#define PCI0_BASE_ADDR		0x18080000
-#define PCI_LBA_COUNT		4
-
-struct pci_map {
-	u32 address;		/* Address. */
-	u32 control;		/* Control. */
-	u32 mapping;		/* mapping. */
-};
-
-struct pci_reg {
-	u32 pcic;
-	u32 pcis;
-	u32 pcism;
-	u32 pcicfga;
-	u32 pcicfgd;
-	volatile struct pci_map pcilba[PCI_LBA_COUNT];
-	u32 pcidac;
-	u32 pcidas;
-	u32 pcidasm;
-	u32 pcidad;
-	u32 pcidma8c;
-	u32 pcidma9c;
-	u32 pcitc;
-};
-
-#define PCI_MSU_COUNT		2
-
-struct pci_msu {
-	u32 pciim[PCI_MSU_COUNT];
-	u32 pciom[PCI_MSU_COUNT];
-	u32 pciid;
-	u32 pciiic;
-	u32 pciiim;
-	u32 pciiod;
-	u32 pciioic;
-	u32 pciioim;
-};
-
-/*
- * PCI Control Register
- */
-
-#define PCI_CTL_EN		(1 << 0)
-#define PCI_CTL_TNR		(1 << 1)
-#define PCI_CTL_SCE		(1 << 2)
-#define PCI_CTL_IEN		(1 << 3)
-#define PCI_CTL_AAA		(1 << 4)
-#define PCI_CTL_EAP		(1 << 5)
-#define PCI_CTL_PCIM_BIT	6
-#define PCI_CTL_PCIM		0x000001c0
-
-#define PCI_CTL_PCIM_DIS	0
-#define PCI_CTL_PCIM_TNR	1 /* Satellite - target not ready */
-#define PCI_CTL_PCIM_SUS	2 /* Satellite - suspended CPU. */
-#define PCI_CTL_PCIM_EXT	3 /* Host - external arbiter. */
-#define PCI_CTL PCIM_PRIO	4 /* Host - fixed priority arb. */
-#define PCI_CTL_PCIM_RR		5 /* Host - round robin priority. */
-#define PCI_CTL_PCIM_RSVD6	6
-#define PCI_CTL_PCIM_RSVD7	7
-
-#define PCI_CTL_IGM		(1 << 9)
-
-/*
- * PCI Status Register
- */
-
-#define PCI_STAT_EED		(1 << 0)
-#define PCI_STAT_WR		(1 << 1)
-#define PCI_STAT_NMI		(1 << 2)
-#define PCI_STAT_II		(1 << 3)
-#define PCI_STAT_CWE		(1 << 4)
-#define PCI_STAT_CRE		(1 << 5)
-#define PCI_STAT_MDPE		(1 << 6)
-#define PCI_STAT_STA		(1 << 7)
-#define PCI_STAT_RTA		(1 << 8)
-#define PCI_STAT_RMA		(1 << 9)
-#define PCI_STAT_SSE		(1 << 10)
-#define PCI_STAT_OSE		(1 << 11)
-#define PCI_STAT_PE		(1 << 12)
-#define PCI_STAT_TAE		(1 << 13)
-#define PCI_STAT_RLE		(1 << 14)
-#define PCI_STAT_BME		(1 << 15)
-#define PCI_STAT_PRD		(1 << 16)
-#define PCI_STAT_RIP		(1 << 17)
-
-/*
- * PCI Status Mask Register
- */
-
-#define PCI_STATM_EED		PCI_STAT_EED
-#define PCI_STATM_WR		PCI_STAT_WR
-#define PCI_STATM_NMI		PCI_STAT_NMI
-#define PCI_STATM_II		PCI_STAT_II
-#define PCI_STATM_CWE		PCI_STAT_CWE
-#define PCI_STATM_CRE		PCI_STAT_CRE
-#define PCI_STATM_MDPE		PCI_STAT_MDPE
-#define PCI_STATM_STA		PCI_STAT_STA
-#define PCI_STATM_RTA		PCI_STAT_RTA
-#define PCI_STATM_RMA		PCI_STAT_RMA
-#define PCI_STATM_SSE		PCI_STAT_SSE
-#define PCI_STATM_OSE		PCI_STAT_OSE
-#define PCI_STATM_PE		PCI_STAT_PE
-#define PCI_STATM_TAE		PCI_STAT_TAE
-#define PCI_STATM_RLE		PCI_STAT_RLE
-#define PCI_STATM_BME		PCI_STAT_BME
-#define PCI_STATM_PRD		PCI_STAT_PRD
-#define PCI_STATM_RIP		PCI_STAT_RIP
-
-/*
- * PCI Configuration Address Register
- */
-#define PCI_CFGA_REG_BIT	2
-#define PCI_CFGA_REG		0x000000fc
-#define	 PCI_CFGA_REG_ID	(0x00 >> 2)	/* use PCFGID */
-#define	 PCI_CFGA_REG_04	(0x04 >> 2)	/* use PCFG04_ */
-#define	 PCI_CFGA_REG_08	(0x08 >> 2)	/* use PCFG08_ */
-#define	 PCI_CFGA_REG_0C	(0x0C >> 2)	/* use PCFG0C_ */
-#define	 PCI_CFGA_REG_PBA0	(0x10 >> 2)	/* use PCIPBA_ */
-#define	 PCI_CFGA_REG_PBA1	(0x14 >> 2)	/* use PCIPBA_ */
-#define	 PCI_CFGA_REG_PBA2	(0x18 >> 2)	/* use PCIPBA_ */
-#define	 PCI_CFGA_REG_PBA3	(0x1c >> 2)	/* use PCIPBA_ */
-#define	 PCI_CFGA_REG_SUBSYS	(0x2c >> 2)	/* use PCFGSS_ */
-#define  PCI_CFGA_REG_3C	(0x3C >> 2)	/* use PCFG3C_ */
-#define	 PCI_CFGA_REG_PBBA0C	(0x44 >> 2)	/* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA0M	(0x48 >> 2)
-#define	 PCI_CFGA_REG_PBA1C	(0x4c >> 2)	/* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA1M	(0x50 >> 2)
-#define	 PCI_CFGA_REG_PBA2C	(0x54 >> 2)	/* use PCIPBAC_ */
-#define	 PCI_CFGA_REG_PBA2M	(0x58 >> 2)
-#define	 PCI_CFGA_REG_PBA3C	(0x5c >> 2)	/* use PCIPBAC_ */
-#define	 PCI_CFGA_REG_PBA3M	(0x60 >> 2)
-#define	 PCI_CFGA_REG_PMGT	(0x64 >> 2)
-#define PCI_CFGA_FUNC_BIT	8
-#define PCI_CFGA_FUNC		0x00000700
-#define PCI_CFGA_DEV_BIT	11
-#define	PCI_CFGA_DEV		0x0000f800
-#define	PCI_CFGA_DEV_INTERN	0
-#define	PCI_CFGA_BUS_BIT	16
-#define PCI CFGA_BUS		0x00ff0000
-#define PCI_CFGA_BUS_TYPE0	0
-#define PCI_CFGA_EN		(1 << 31)
-
-/* PCI CFG04 commands */
-#define PCI_CFG04_CMD_IO_ENA	(1 << 0)
-#define PCI_CFG04_CMD_MEM_ENA	(1 << 1)
-#define PCI_CFG04_CMD_BM_ENA	(1 << 2)
-#define PCI_CFG04_CMD_MW_INV	(1 << 4)
-#define PCI_CFG04_CMD_PAR_ENA	(1 << 6)
-#define PCI_CFG04_CMD_SER_ENA	(1 << 8)
-#define PCI_CFG04_CMD_FAST_ENA	(1 << 9)
-
-/* PCI CFG04 status fields */
-#define PCI_CFG04_STAT_BIT	16
-#define PCI_CFG04_STAT		0xffff0000
-#define PCI_CFG04_STAT_66_MHZ	(1 << 21)
-#define PCI_CFG04_STAT_FBB	(1 << 23)
-#define PCI_CFG04_STAT_MDPE	(1 << 24)
-#define PCI_CFG04_STAT_DST	(1 << 25)
-#define PCI_CFG04_STAT_STA	(1 << 27)
-#define PCI_CFG04_STAT_RTA	(1 << 28)
-#define PCI_CFG04_STAT_RMA	(1 << 29)
-#define PCI_CFG04_STAT_SSE	(1 << 30)
-#define PCI_CFG04_STAT_PE	(1 << 31)
-
-#define PCI_PBA_MSI		(1 << 0)
-#define PCI_PBA_P		(1 << 2)
-
-/* PCI PBAC registers */
-#define PCI_PBAC_MSI		(1 << 0)
-#define PCI_PBAC_P		(1 << 1)
-#define PCI_PBAC_SIZE_BIT	2
-#define PCI_PBAC_SIZE		0x0000007c
-#define	PCI_PBAC_SB		(1 << 7)
-#define	PCI_PBAC_PP		(1 << 8)
-#define PCI_PBAC_MR_BIT		9
-#define PCI_PBAC_MR		0x00000600
-#define	 PCI_PBAC_MR_RD		0
-#define	 PCI_PBAC_MR_RD_LINE	1
-#define  PCI_PBAC_MR_RD_MULT	2
-#define PCI_PBAC_MRL		(1 << 11)
-#define PCI_PBAC_MRM		(1 << 12)
-#define PCI_PBAC_TRP		(1 << 13)
-
-#define PCI_CFG40_TRDY_TIM	0x000000ff
-#define PCI_CFG40_RET_LIM	0x0000ff00
-
-/*
- * PCI Local Base Address [0|1|2|3] Register
- */
-
-#define PCI_LBA_BADDR_BIT	0
-#define PCI_LBA_BADDR		0xffffff00
-
-/*
- * PCI Local Base Address Control Register
- */
-
-#define PCI_LBAC_MSI		(1 << 0)
-#define  PCI_LBAC_MSI_MEM	0
-#define  PCI_LBAC_MSI_IO	1
-#define PCI_LBAC_SIZE_BIT	2
-#define PCI_LBAC_SIZE		0x0000007c
-#define PCI_LBAC_SB		(1 << 7)
-#define PCI_LBAC_RT		(1 << 8)
-#define  PCI_LBAC_RT_NO_PREF	0
-#define  PCI_LBAC_RT_PREF	1
-
-/*
- * PCI Local Base Address [0|1|2|3] Mapping Register
- */
-#define PCI_LBAM_MADDR_BIT	8
-#define PCI_LBAM_MADDR		0xffffff00
-
-/*
- * PCI Decoupled Access Control Register
- */
-#define PCI_DAC_DEN		(1 << 0)
-
-/*
- * PCI Decoupled Access Status Register
- */
-#define PCI_DAS_D		(1 << 0)
-#define PCI_DAS_B		(1 << 1)
-#define PCI_DAS_E		(1 << 2)
-#define PCI_DAS_OFE		(1 << 3)
-#define PCI_DAS_OFF		(1 << 4)
-#define PCI_DAS_IFE		(1 << 5)
-#define PCI_DAS_IFF		(1 << 6)
-
-/*
- * PCI DMA Channel 8 Configuration Register
- */
-#define PCI_DMA8C_MBS_BIT	0
-#define PCI_DMA8C_MBS		0x00000fff /* Maximum Burst Size. */
-#define PCI_DMA8C_OUR		(1 << 12)
-
-/*
- * PCI DMA Channel 9 Configuration Register
- */
-#define PCI_DMA9C_MBS_BIT	0	/* Maximum Burst Size. */
-#define PCI_DMA9C_MBS		0x00000fff
-
-/*
- * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
- */
-
-#define PCI_DMAD_PT_BIT		22		/* in DEVCMD field (descriptor) */
-#define PCI_DMAD_PT		0x00c00000	/* preferred transaction field */
-/* These are for reads (DMA channel 8) */
-#define PCI_DMAD_DEVCMD_MR	0		/* memory read */
-#define	PCI_DMAD_DEVCMD_MRL	1		/* memory read line */
-#define	PCI_DMAD_DEVCMD_MRM	2		/* memory read multiple */
-#define	PCI_DMAD_DEVCMD_IOR	3		/* I/O read */
-/* These are for writes (DMA channel 9) */
-#define PCI_DMAD_DEVCMD_MW	0		/* memory write */
-#define	PCI_DMAD_DEVCMD_MWI	1		/* memory write invalidate */
-#define	PCI_DMAD_DEVCMD_IOW	3		/* I/O write */
-
-/* Swap byte field applies to both DMA channel 8 and 9 */
-#define	PCI_DMAD_SB		(1 << 24)	/* swap byte field */
-
-
-/*
- * PCI Target Control Register
- */
-
-#define PCI_TC_RTIMER_BIT	0
-#define PCI_TC_RTIMER		0x000000ff
-#define PCI_TC_DTIMER_BIT	8
-#define PCI_TC_DTIMER		0x0000ff00
-#define PCI_TC_RDR		(1 << 18)
-#define PCI_TC_DDT		(1 << 19)
-
-/*
- * PCI messaging unit [applies to both inbound and outbound registers ]
- */
-#define PCI_MSU_M0		(1 << 0)
-#define PCI_MSU_M1		(1 << 1)
-#define PCI_MSU_DB		(1 << 2)
-
-#define PCI_MSG_ADDR	     	0xB8088010
-#define PCI0_ADDR		0xB8080000
-#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
-#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
-
-#define PCIM_SHFT		0x6
-#define PCIM_BIT_LEN		0x7
-#define PCIM_H_EA		0x3
-#define PCIM_H_IA_FIX		0x4
-#define PCIM_H_IA_RR		0x5
-#if 0
-#define PCI_ADDR_START		0x13000000
-#endif
-
-#define PCI_ADDR_START		0x50000000
-
-#define CPUTOPCI_MEM_WIN	0x02000000
-#define CPUTOPCI_IO_WIN		0x00100000
-#define PCILBA_SIZE_SHFT	2
-#define PCILBA_SIZE_MASK	0x1F
-#define SIZE_256MB		0x1C
-#define SIZE_128MB		0x1B
-#define SIZE_64MB               0x1A
-#define SIZE_32MB		0x19
-#define SIZE_16MB               0x18
-#define SIZE_4MB		0x16
-#define SIZE_2MB		0x15
-#define SIZE_1MB		0x14
-#define KORINA_CONFIG0_ADDR	0x80000000
-#define KORINA_CONFIG1_ADDR	0x80000004
-#define KORINA_CONFIG2_ADDR	0x80000008
-#define KORINA_CONFIG3_ADDR	0x8000000C
-#define KORINA_CONFIG4_ADDR	0x80000010
-#define KORINA_CONFIG5_ADDR	0x80000014
-#define KORINA_CONFIG6_ADDR	0x80000018
-#define KORINA_CONFIG7_ADDR	0x8000001C
-#define KORINA_CONFIG8_ADDR	0x80000020
-#define KORINA_CONFIG9_ADDR	0x80000024
-#define KORINA_CONFIG10_ADDR	0x80000028
-#define KORINA_CONFIG11_ADDR	0x8000002C
-#define KORINA_CONFIG12_ADDR	0x80000030
-#define KORINA_CONFIG13_ADDR	0x80000034
-#define KORINA_CONFIG14_ADDR	0x80000038
-#define KORINA_CONFIG15_ADDR	0x8000003C
-#define KORINA_CONFIG16_ADDR	0x80000040
-#define KORINA_CONFIG17_ADDR	0x80000044
-#define KORINA_CONFIG18_ADDR	0x80000048
-#define KORINA_CONFIG19_ADDR	0x8000004C
-#define KORINA_CONFIG20_ADDR	0x80000050
-#define KORINA_CONFIG21_ADDR	0x80000054
-#define KORINA_CONFIG22_ADDR	0x80000058
-#define KORINA_CONFIG23_ADDR	0x8000005C
-#define KORINA_CONFIG24_ADDR	0x80000060
-#define KORINA_CONFIG25_ADDR	0x80000064
-#define KORINA_CMD 		(PCI_CFG04_CMD_IO_ENA | \
-				 PCI_CFG04_CMD_MEM_ENA | \
-				 PCI_CFG04_CMD_BM_ENA | \
-				 PCI_CFG04_CMD_MW_INV | \
-				 PCI_CFG04_CMD_PAR_ENA | \
-				 PCI_CFG04_CMD_SER_ENA)
-
-#define KORINA_STAT		(PCI_CFG04_STAT_MDPE | \
-				 PCI_CFG04_STAT_STA | \
-				 PCI_CFG04_STAT_RTA | \
-				 PCI_CFG04_STAT_RMA | \
-				 PCI_CFG04_STAT_SSE | \
-				 PCI_CFG04_STAT_PE)
-
-#define KORINA_CNFG1		((KORINA_STAT<<16)|KORINA_CMD)
-
-#define KORINA_REVID		0
-#define KORINA_CLASS_CODE	0
-#define KORINA_CNFG2		((KORINA_CLASS_CODE<<8) | \
-				  KORINA_REVID)
-
-#define KORINA_CACHE_LINE_SIZE	4
-#define KORINA_MASTER_LAT	0x3c
-#define KORINA_HEADER_TYPE	0
-#define KORINA_BIST		0
-
-#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
-		      (KORINA_HEADER_TYPE<<16) | \
-		      (KORINA_MASTER_LAT<<8) | \
-		      KORINA_CACHE_LINE_SIZE)
-
-#define KORINA_BAR0	0x00000008	/* 128 MB Memory */
-#define KORINA_BAR1	0x18800001	/* 1 MB IO */
-#define KORINA_BAR2	0x18000001	/* 2 MB IO window for Korina
-					   internal Registers */
-#define KORINA_BAR3	0x48000008	/* Spare 128 MB Memory */
-
-#define KORINA_CNFG4	KORINA_BAR0
-#define KORINA_CNFG5    KORINA_BAR1
-#define KORINA_CNFG6 	KORINA_BAR2
-#define KORINA_CNFG7	KORINA_BAR3
-
-#define KORINA_SUBSYS_VENDOR_ID 0x011d
-#define KORINA_SUBSYSTEM_ID	0x0214
-#define KORINA_CNFG8		0
-#define KORINA_CNFG9		0
-#define KORINA_CNFG10		0
-#define KORINA_CNFG11 	((KORINA_SUBSYS_VENDOR_ID<<16) | \
-			  KORINA_SUBSYSTEM_ID)
-#define KORINA_INT_LINE		1
-#define KORINA_INT_PIN		1
-#define KORINA_MIN_GNT		8
-#define KORINA_MAX_LAT		0x38
-#define KORINA_CNFG12		0
-#define KORINA_CNFG13 		0
-#define KORINA_CNFG14		0
-#define KORINA_CNFG15	((KORINA_MAX_LAT<<24) | \
-			 (KORINA_MIN_GNT<<16) | \
-			 (KORINA_INT_PIN<<8)  | \
-			  KORINA_INT_LINE)
-#define	KORINA_RETRY_LIMIT	0x80
-#define KORINA_TRDY_LIMIT	0x80
-#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
-			KORINA_TRDY_LIMIT)
-#define PCI_PBAxC_R		0x0
-#define PCI_PBAxC_RL		0x1
-#define PCI_PBAxC_RM		0x2
-#define SIZE_SHFT		2
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA0C	(PCI_PBAC_MRL | PCI_PBAC_SB | \
-			  ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
-			  PCI_PBAC_PP | \
-			  (SIZE_128MB<<SIZE_SHFT) | \
-			   PCI_PBAC_P)
-#else
-#define KORINA_PBA0C	(PCI_PBAC_MRL | \
-			  ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
-			  PCI_PBAC_PP | \
-			  (SIZE_128MB<<SIZE_SHFT) | \
-			   PCI_PBAC_P)
-#endif
-#define KORINA_CNFG17	KORINA_PBA0C
-#define KORINA_PBA0M	0x0
-#define KORINA_CNFG18	KORINA_PBA0M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA1C	((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
-			  PCI_PBAC_MSI)
-#else
-#define KORINA_PBA1C	((SIZE_1MB<<SIZE_SHFT) | \
-			  PCI_PBAC_MSI)
-#endif
-#define KORINA_CNFG19	KORINA_PBA1C
-#define KORINA_PBA1M	0x0
-#define KORINA_CNFG20	KORINA_PBA1M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA2C	((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
-			  PCI_PBAC_MSI)
-#else
-#define KORINA_PBA2C	((SIZE_2MB<<SIZE_SHFT) | \
-			  PCI_PBAC_MSI)
-#endif
-#define KORINA_CNFG21	KORINA_PBA2C
-#define KORINA_PBA2M	0x18000000
-#define KORINA_CNFG22	KORINA_PBA2M
-#define KORINA_PBA3C	0
-#define KORINA_CNFG23	KORINA_PBA3C
-#define KORINA_PBA3M	0
-#define KORINA_CNFG24	KORINA_PBA3M
-
-#define	PCITC_DTIMER_VAL	8
-#define PCITC_RTIMER_VAL	0x10
-
-#endif  /* __ASM_RC32434_PCI_H */
diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
deleted file mode 100644
index 1d66ddcda89..00000000000
--- a/include/asm-mips/mach-rc32434/prom.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- *  Definitions for the PROM
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#define PROM_ENTRY(x)		(0xbfc00000 + ((x) * 8))
-
-#define GPIO_INIT_NOBUTTON	""
-#define GPIO_INIT_BUTTON	" 2"
-
-#define SR_NMI			0x00180000
-#define SERIAL_SPEED_ENTRY	0x00000001
-
-#define FREQ_TAG		"HZ="
-#define GPIO_TAG		"gpio="
-#define KMAC_TAG		"kmac="
-#define MEM_TAG			"mem="
-#define BOARD_TAG		"board="
-
-#define BOARD_RB532		"500"
-#define BOARD_RB532A		"500r5"
diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
deleted file mode 100644
index e0a76e3ffea..00000000000
--- a/include/asm-mips/mach-rc32434/rb.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *  GNU General Public License for more details.
- *
- *  Copyright (C) 2004 IDT Inc.
- *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- */
-#ifndef __ASM_RC32434_RB_H
-#define __ASM_RC32434_RB_H
-
-#include <linux/genhd.h>
-
-#define IDT434_REG_BASE	((volatile void *) KSEG1ADDR(0x18000000))
-#define DEV0BASE	0x010000
-#define DEV0MASK	0x010004
-#define DEV0C		0x010008
-#define DEV0T		0x01000C
-#define DEV1BASE	0x010010
-#define DEV1MASK	0x010014
-#define DEV1C		0x010018
-#define DEV1TC		0x01001C
-#define DEV2BASE	0x010020
-#define DEV2MASK	0x010024
-#define DEV2C		0x010028
-#define DEV2TC		0x01002C
-#define DEV3BASE	0x010030
-#define DEV3MASK	0x010034
-#define DEV3C		0x010038
-#define DEV3TC		0x01003C
-#define BTCS		0x010040
-#define BTCOMPARE	0x010044
-#define GPIOBASE	0x050000
-#define GPIOCFG		0x050004
-#define GPIOD		0x050008
-#define GPIOILEVEL	0x05000C
-#define GPIOISTAT	0x050010
-#define GPIONMIEN	0x050014
-#define IMASK6		0x038038
-#define LO_WPX		(1 << 0)
-#define LO_ALE		(1 << 1)
-#define LO_CLE		(1 << 2)
-#define LO_CEX		(1 << 3)
-#define LO_FOFF		(1 << 5)
-#define LO_SPICS	(1 << 6)
-#define LO_ULED		(1 << 7)
-
-#define BIT_TO_MASK(x)	(1 << x)
-
-struct dev_reg {
-	u32	base;
-	u32	mask;
-	u32	ctl;
-	u32	timing;
-};
-
-struct korina_device {
-	char *name;
-	unsigned char mac[6];
-	struct net_device *dev;
-};
-
-struct cf_device {
-	int gpio_pin;
-	void *dev;
-	struct gendisk *gd;
-};
-
-struct mpmc_device {
-	unsigned char	state;
-	spinlock_t	lock;
-	void __iomem 	*base;
-};
-
-#endif  /* __ASM_RC32434_RB_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
deleted file mode 100644
index c4a02145104..00000000000
--- a/include/asm-mips/mach-rc32434/rc32434.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Definitions for IDT RC323434 CPU.
- */
-
-#ifndef _ASM_RC32434_RC32434_H_
-#define _ASM_RC32434_RC32434_H_
-
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#define RC32434_REG_BASE	0x18000000
-#define RC32434_RST		(1 << 15)
-
-#define IDT_CLOCK_MULT		2
-#define MIPS_CPU_TIMER_IRQ	7
-
-/* Interrupt Controller */
-#define IC_GROUP0_PEND		(RC32434_REG_BASE + 0x38000)
-#define IC_GROUP0_MASK		(RC32434_REG_BASE + 0x38008)
-#define IC_GROUP_OFFSET		0x0C
-
-#define NUM_INTR_GROUPS		5
-
-/* 16550 UARTs */
-#define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */
-					/* GRP3 IRQ numbers start here */
-#define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32)
-					/* GRP4 IRQ numbers start here */
-#define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32)
-					/* GRP5 IRQ numbers start here */
-#define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32)
-#define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32)
-
-
-#ifdef __MIPSEB__
-#define RC32434_UART0_BASE	(RC32434_REG_BASE + 0x58003)
-#else
-#define RC32434_UART0_BASE	(RC32434_REG_BASE + 0x58000)
-#endif
-
-#define RC32434_UART0_IRQ	(GROUP3_IRQ_BASE + 0)
-
-/* cpu pipeline flush */
-static inline void rc32434_sync(void)
-{
-	__asm__ volatile ("sync");
-}
-
-static inline void rc32434_sync_udelay(int us)
-{
-	__asm__ volatile ("sync");
-	udelay(us);
-}
-
-static inline void rc32434_sync_delay(int ms)
-{
-	__asm__ volatile ("sync");
-	mdelay(ms);
-}
-
-#endif  /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h
deleted file mode 100644
index e49b1d57a01..00000000000
--- a/include/asm-mips/mach-rc32434/timer.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- *  Definitions for timer registers
- *
- *  Copyright 2004 Philip Rischel <rischelp@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_RC32434_TIMER_H
-#define __ASM_RC32434_TIMER_H
-
-#include <asm/mach-rc32434/rb.h>
-
-#define TIMER0_BASE_ADDR		0x18028000
-#define TIMER_COUNT			3
-
-struct timer_counter {
-	u32 count;
-	u32 compare;
-	u32 ctc;		/*use CTC_ */
-};
-
-struct timer {
-	struct timer_counter tim[TIMER_COUNT];
-	u32 rcount;	/* use RCOUNT_ */
-	u32 rcompare;	/* use RCOMPARE_ */
-	u32 rtc;	/* use RTC_ */
-};
-
-#define RC32434_CTC_EN_BIT		0
-#define RC32434_CTC_TO_BIT		1
-
-/* Real time clock registers */
-#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
-#define RC32434_RTC_CE_BIT              0
-#define RC32434_RTC_TO_BIT              1
-#define RC32434_RTC_RQE_BIT             2
-
-/* Counter registers */
-#define RC32434_RCOUNT_BIT              0
-#define RC32434_RCOUNT_MSK              0x0000ffff
-#define RC32434_RCOMP_BIT               0
-#define RC32434_RCOMP_MSK               0x0000ffff
-
-#endif  /* __ASM_RC32434_TIMER_H */
diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h
deleted file mode 100644
index 3ddf187e98a..00000000000
--- a/include/asm-mips/mach-rc32434/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR	0
-#define R4600_V1_HIT_CACHEOP_WAR	0
-#define R4600_V2_HIT_CACHEOP_WAR	0
-#define R5432_CP0_INTERRUPT_WAR		0
-#define BCM1250_M3_WAR			0
-#define SIBYTE_1956_WAR			0
-#define MIPS4K_ICACHE_REFILL_WAR	1
-#define MIPS_CACHE_SYNC_WAR		0
-#define TX49XX_ICACHE_INDEX_INV_WAR	0
-#define RM9000_CDEX_SMP_WAR		0
-#define ICACHE_REFILLS_WORKAROUND_WAR	0
-#define R10000_LLSC_WAR			0
-#define MIPS34K_MISSED_ITLB_WAR		0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */