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authorBen Skeggs <bskeggs@redhat.com>2011-10-19 14:06:59 +1000
committerBen Skeggs <bskeggs@redhat.com>2011-11-10 08:59:47 +1000
commit2bfa7482224903097a50c14a4389a29f56e19c3b (patch)
treef27c3cb366dbe305ba5c4cc06b695a6d236886ff /drivers
parentef5ced4bfe48ba2acb16e867ceb9c473dd0ef192 (diff)
drm/nv40/pm: fix issues on igp chipsets, which don't have memory
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/nv40_pm.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c
index bbc0b9c7e1f..e676b0d5347 100644
--- a/drivers/gpu/drm/nouveau/nv40_pm.c
+++ b/drivers/gpu/drm/nouveau/nv40_pm.c
@@ -57,12 +57,14 @@ read_pll_2(struct drm_device *dev, u32 reg)
int P = (ctrl & 0x00070000) >> 16;
u32 ref = 27000, clk = 0;
- if (ctrl & 0x80000000)
+ if ((ctrl & 0x80000000) && M1) {
clk = ref * N1 / M1;
-
- if (!(ctrl & 0x00000100)) {
- if (ctrl & 0x40000000)
- clk = clk * N2 / M2;
+ if ((ctrl & 0x40000100) == 0x40000000) {
+ if (M2)
+ clk = clk * N2 / M2;
+ else
+ clk = 0;
+ }
}
return clk >> P;
@@ -177,6 +179,11 @@ nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
}
/* memory clock */
+ if (!perflvl->memory) {
+ info->mpll_ctrl = 0x00000000;
+ goto out;
+ }
+
ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
@@ -264,6 +271,9 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
mdelay(5);
nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);
+ if (!info->mpll_ctrl)
+ goto resume;
+
/* wait for vblank start on active crtcs, disable memory access */
for (i = 0; i < 2; i++) {
if (!(crtc_mask & (1 << i)))