diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2011-05-19 12:12:46 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-05-19 18:00:00 -0400 |
| commit | 1ff30a59f6d0c754e99442501a5145bdbbcfa6ea (patch) | |
| tree | 28c1fb69dea98daba406fc07c6df0edd04cbbba5 /drivers | |
| parent | 432aa7ed75b3adaef6040d2cbe745fdd1c899415 (diff) | |
tg3: Fix 57765 B0 data corruption
The PCIe max FTS limit is too aggressive on these chips. This patch
loosens the limit a little to eliminate data corruption issues.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tg3.c | 16 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 4 |
2 files changed, 20 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b2b1ba168c8..09f2c11db24 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7990,6 +7990,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(GRC_MODE, grc_mode); } + if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { + u32 grc_mode = tr32(GRC_MODE); + + /* Access the lower 1K of DL PCIE block registers. */ + val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; + tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); + + val = tr32(TG3_PCIE_TLDLPL_PORT + + TG3_PCIE_DL_LO_FTSMAX); + val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; + tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, + val | TG3_PCIE_DL_LO_FTSMAX_VAL); + + tw32(GRC_MODE, grc_mode); + } + val = tr32(TG3_CPMU_LSPD_10MB_CLK); val &= ~CPMU_LSPD_10MB_MACCLK_MASK; val |= CPMU_LSPD_10MB_MACCLK_6_25; diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index ce010cd3389..330959b9cfb 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -180,6 +180,7 @@ #define CHIPREV_5750_BX 0x41 #define CHIPREV_5784_AX 0x57840 #define CHIPREV_5761_AX 0x57610 +#define CHIPREV_57765_AX 0x577650 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) #define METAL_REV_A0 0x00 #define METAL_REV_A1 0x01 @@ -1951,6 +1952,9 @@ /* Alternate PCIE definitions */ #define TG3_PCIE_TLDLPL_PORT 0x00007c00 +#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c +#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff +#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 |