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authorBjorn Helgaas <bhelgaas@google.com>2013-04-17 16:57:56 -0600
committerBjorn Helgaas <bhelgaas@google.com>2013-04-23 09:50:30 -0600
commit703860ed4e36ded696bd44af6107243fdedfb746 (patch)
treeeb5bd366144a03639ac8ae229c571381a1c98e96 /drivers
parent99369065970e9ea7d1ca489341ed29d1a72ec0b5 (diff)
PCI: Use u8, not int, for PM capability offset
The Power Management Capability (PCI_CAP_ID_PM == 0x01) is defined by PCI and must appear in the 256-byte PCI Configuration Space from 0-0xff. It cannot be in the PCIe Extended Configuration space from 0x100-0xfff, so we only need a u8 to hold its offset. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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