diff options
| author | Andrew Bresticker <abrestic@chromium.org> | 2013-12-26 16:44:26 -0800 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-02-17 16:18:28 +0200 |
| commit | 88b4bd7071ac06e321b4bf4bdb8c69db40182c5a (patch) | |
| tree | d7eb0c0bb43d499be95386347f6560a08b17ff95 /drivers | |
| parent | 20e7c323abac390deb35248705807bd844590048 (diff) | |
clk: tegra: cclk_lp has a pllx/2 divider
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-super-gen4.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index 05dce4aa2c1..feb3201c85c 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, ARRAY_SIZE(cclk_lp_parents), CLK_SET_RATE_PARENT, clk_base + CCLKLP_BURST_POLICY, - 0, 4, 8, 9, NULL); + TEGRA_DIVIDER_2, 4, 8, 9, NULL); *dt_clk = clk; } |