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authorAlex Deucher <alexdeucher@gmail.com>2010-08-19 11:19:31 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-08-26 16:46:21 -0700
commit410ff49be76bfef96889b1e4718bf1bc2048a636 (patch)
tree526be41fe594ca9541b4968bc4f90c172f41d385 /drivers
parenta9982269c438c05742a58636165700f6fe0c38db (diff)
drm/radeon/kms/DCE3+: switch pads to ddc mode when going i2c
commit 5786e2c5a3f519647c50bbc276e45d36a704415a upstream. The pins for ddc and aux are shared so you need to switch the mode when doing ddc. The ProcessAuxChannel table already sets the pin mode to DP. This should fix unreliable ddc issues on DP ports using non-DP monitors. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 5def6f5dff3..0cd2704e9a4 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -95,6 +95,13 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
}
}
+ /* switch the pads to ddc mode */
+ if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
+ temp = RREG32(rec->mask_clk_reg);
+ temp &= ~(1 << 16);
+ WREG32(rec->mask_clk_reg, temp);
+ }
+
/* clear the output pin values */
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
WREG32(rec->a_clk_reg, temp);