diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2012-09-18 14:51:46 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 23:34:03 +1000 |
| commit | 944c3d81dbead14725e7d12675c37a2027760608 (patch) | |
| tree | 3531830148ee9ec29bb590c356aca1e3ae25655c /drivers/watchdog | |
| parent | 632306f2454bf46c71d4fb7a499916d942b22a32 (diff) | |
m68knommu: clean up ColdFire 54xx General Timer definitions
Convert the ColdFire 54xx CPU General Timer register address definitions to
include the MCF_MBAR peripheral region offset. This makes them consistent
with all other 54xx address register definitions (in m54xxsim.h).
The goal is to reduce different definitions used (some including offsets and
others not) causing bugs when used incorrectly.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/m54xx_wdt.c | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/drivers/watchdog/m54xx_wdt.c b/drivers/watchdog/m54xx_wdt.c index 663cad86c63..173494a681e 100644 --- a/drivers/watchdog/m54xx_wdt.c +++ b/drivers/watchdog/m54xx_wdt.c @@ -46,17 +46,17 @@ static void wdt_enable(void) unsigned int gms0; /* preserve GPIO usage, if any */ - gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); + gms0 = __raw_readl(MCF_GPT_GMS0); if (gms0 & MCF_GPT_GMS_TMS_GPIO) gms0 &= (MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_GPIO_MASK | MCF_GPT_GMS_OD); else gms0 = MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_OD; - __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(gms0, MCF_GPT_GMS0); __raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) | - MCF_GPT_GCIR_CNT(0xffff), MCF_MBAR + MCF_GPT_GCIR0); + MCF_GPT_GCIR_CNT(0xffff), MCF_GPT_GCIR0); gms0 |= MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE; - __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(gms0, MCF_GPT_GMS0); } static void wdt_disable(void) @@ -64,18 +64,18 @@ static void wdt_disable(void) unsigned int gms0; /* disable watchdog */ - gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); + gms0 = __raw_readl(MCF_GPT_GMS0); gms0 &= ~(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE); - __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(gms0, MCF_GPT_GMS0); } static void wdt_keepalive(void) { unsigned int gms0; - gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); + gms0 = __raw_readl(MCF_GPT_GMS0); gms0 |= MCF_GPT_GMS_OCPW(0xA5); - __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(gms0, MCF_GPT_GMS0); } static int m54xx_wdt_open(struct inode *inode, struct file *file) @@ -195,8 +195,7 @@ static struct miscdevice m54xx_wdt_miscdev = { static int __init m54xx_wdt_init(void) { - if (!request_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4, - "Coldfire M54xx Watchdog")) { + if (!request_mem_region(MCF_GPT_GCIR0, 4, "Coldfire M54xx Watchdog")) { pr_warn("I/O region busy\n"); return -EBUSY; } @@ -208,7 +207,7 @@ static int __init m54xx_wdt_init(void) static void __exit m54xx_wdt_exit(void) { misc_deregister(&m54xx_wdt_miscdev); - release_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4); + release_mem_region(MCF_GPT_GCIR0, 4); } module_init(m54xx_wdt_init); |