Merge branch 'sh/platform-updates' into sh-latest

97 files changed, 5888 insertions, 5533 deletions

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967e4e1..6ca0c407c14 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1763,16 +1763,16 @@ config FB_AU1100
 	  au1100fb:panel=<name>.
 
 config FB_AU1200
-	bool "Au1200 LCD Driver"
+	bool "Au1200/Au1300 LCD Driver"
 	depends on (FB = y) && MIPS_ALCHEMY
 	select FB_SYS_FILLRECT
 	select FB_SYS_COPYAREA
 	select FB_SYS_IMAGEBLIT
 	select FB_SYS_FOPS
 	help
-	  This is the framebuffer driver for the AMD Au1200 SOC.  It can drive
-	  various panels and CRTs by passing in kernel cmd line option
-	  au1200fb:panel=<name>.
+	  This is the framebuffer driver for the Au1200/Au1300 SOCs.
+	  It can drive various panels and CRTs by passing in kernel cmd line
+	  option au1200fb:panel=<name>.
 
 config FB_VT8500
 	bool "VT8500 LCD Driver"
@@ -2413,7 +2413,6 @@ source "drivers/video/omap/Kconfig"
 source "drivers/video/omap2/Kconfig"
 
 source "drivers/video/backlight/Kconfig"
-source "drivers/video/display/Kconfig"
 
 if VT
 	source "drivers/video/console/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b9d8fff773..142606814d9 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -13,7 +13,7 @@ fb-objs                           := $(fb-y)
 
 obj-$(CONFIG_VT)		  += console/
 obj-$(CONFIG_LOGO)		  += logo/
-obj-y				  += backlight/ display/
+obj-y				  += backlight/
 
 obj-$(CONFIG_FB_CFB_FILLRECT)  += cfbfillrect.o
 obj-$(CONFIG_FB_CFB_COPYAREA)  += cfbcopyarea.o
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c
index 5ea6596dd82..f23cae094f1 100644
--- a/drivers/video/amifb.c
+++ b/drivers/video/amifb.c
@@ -152,10 +152,10 @@
 
       - hsstrt:   Start of horizontal synchronization pulse
       - hsstop:   End of horizontal synchronization pulse
-      - htotal:   Last value on the line (i.e. line length = htotal+1)
+      - htotal:   Last value on the line (i.e. line length = htotal + 1)
       - vsstrt:   Start of vertical synchronization pulse
       - vsstop:   End of vertical synchronization pulse
-      - vtotal:   Last line value (i.e. number of lines = vtotal+1)
+      - vtotal:   Last line value (i.e. number of lines = vtotal + 1)
       - hcenter:  Start of vertical retrace for interlace
 
    You can specify the blanking timings independently. Currently I just set
@@ -184,7 +184,7 @@
    clock):
 
       - diwstrt_h:   Horizontal start of the visible window
-      - diwstop_h:   Horizontal stop+1(*) of the visible window
+      - diwstop_h:   Horizontal stop + 1(*) of the visible window
       - diwstrt_v:   Vertical start of the visible window
       - diwstop_v:   Vertical stop of the visible window
       - ddfstrt:     Horizontal start of display DMA
@@ -193,7 +193,7 @@
 
    Sprite positioning:
 
-      - sprstrt_h:   Horizontal start-4 of sprite
+      - sprstrt_h:   Horizontal start - 4 of sprite
       - sprstrt_v:   Vertical start of sprite
 
    (*) Even Commodore did it wrong in the AGA monitor drivers by not adding 1.
@@ -212,21 +212,21 @@
    display parameters. Here's what I found out:
 
       - ddfstrt and ddfstop are best aligned to 64 pixels.
-      - the chipset needs 64+4 horizontal pixels after the DMA start before the
-        first pixel is output, so diwstrt_h = ddfstrt+64+4 if you want to
-        display the first pixel on the line too. Increase diwstrt_h for virtual
-        screen panning.
+      - the chipset needs 64 + 4 horizontal pixels after the DMA start before
+	the first pixel is output, so diwstrt_h = ddfstrt + 64 + 4 if you want
+	to display the first pixel on the line too. Increase diwstrt_h for
+	virtual screen panning.
       - the display DMA always fetches 64 pixels at a time (fmode = 3).
-      - ddfstop is ddfstrt+#pixels-64.
-      - diwstop_h = diwstrt_h+xres+1. Because of the additional 1 this can be 1
-        more than htotal.
+      - ddfstop is ddfstrt+#pixels - 64.
+      - diwstop_h = diwstrt_h + xres + 1. Because of the additional 1 this can
+	be 1 more than htotal.
       - hscroll simply adds a delay to the display output. Smooth horizontal
-        panning needs an extra 64 pixels on the left to prefetch the pixels that
-        `fall off' on the left.
+	panning needs an extra 64 pixels on the left to prefetch the pixels that
+	`fall off' on the left.
       - if ddfstrt < 192, the sprite DMA cycles are all stolen by the bitplane
-        DMA, so it's best to make the DMA start as late as possible.
+	DMA, so it's best to make the DMA start as late as possible.
       - you really don't want to make ddfstrt < 128, since this will steal DMA
-        cycles from the other DMA channels (audio, floppy and Chip RAM refresh).
+	cycles from the other DMA channels (audio, floppy and Chip RAM refresh).
       - I make diwstop_h and diwstop_v as large as possible.
 
    General dependencies
@@ -234,8 +234,8 @@
 
       - all values are SHRES pixel (35ns)
 
-                  table 1:fetchstart  table 2:prefetch    table 3:fetchsize
-                  ------------------  ----------------    -----------------
+		  table 1:fetchstart  table 2:prefetch    table 3:fetchsize
+		  ------------------  ----------------    -----------------
    Pixclock     # SHRES|HIRES|LORES # SHRES|HIRES|LORES # SHRES|HIRES|LORES
    -------------#------+-----+------#------+-----+------#------+-----+------
    Bus width 1x #   16 |  32 |  64  #   16 |  32 |  64  #   64 |  64 |  64
@@ -245,21 +245,21 @@
       - chipset needs 4 pixels before the first pixel is output
       - ddfstrt must be aligned to fetchstart (table 1)
       - chipset needs also prefetch (table 2) to get first pixel data, so
-        ddfstrt = ((diwstrt_h-4) & -fetchstart) - prefetch
+	ddfstrt = ((diwstrt_h - 4) & -fetchstart) - prefetch
       - for horizontal panning decrease diwstrt_h
       - the length of a fetchline must be aligned to fetchsize (table 3)
       - if fetchstart is smaller than fetchsize, then ddfstrt can a little bit
-        moved to optimize use of dma (useful for OCS/ECS overscan displays)
-      - ddfstop is ddfstrt+ddfsize-fetchsize
+	moved to optimize use of dma (useful for OCS/ECS overscan displays)
+      - ddfstop is ddfstrt + ddfsize - fetchsize
       - If C= didn't change anything for AGA, then at following positions the
-        dma bus is already used:
-        ddfstrt <  48 -> memory refresh
-                <  96 -> disk dma
-                < 160 -> audio dma
-                < 192 -> sprite 0 dma
-                < 416 -> sprite dma (32 per sprite)
+	dma bus is already used:
+	ddfstrt <  48 -> memory refresh
+		<  96 -> disk dma
+		< 160 -> audio dma
+		< 192 -> sprite 0 dma
+		< 416 -> sprite dma (32 per sprite)
       - in accordance with the hardware reference manual a hardware stop is at
-        192, but AGA (ECS?) can go below this.
+	192, but AGA (ECS?) can go below this.
 
    DMA priorities
    --------------
@@ -269,7 +269,7 @@
    the hardware cursor:
 
       - if you want to start display DMA too early, you lose the ability to
-        do smooth horizontal panning (xpanstep 1 -> 64).
+	do smooth horizontal panning (xpanstep 1 -> 64).
       - if you want to go even further, you lose the hardware cursor too.
 
    IMHO a hardware cursor is more important for X than horizontal scrolling,
@@ -286,8 +286,8 @@
    Standard VGA timings
    --------------------
 
-               xres  yres    left  right  upper  lower    hsync    vsync
-               ----  ----    ----  -----  -----  -----    -----    -----
+	       xres  yres    left  right  upper  lower    hsync    vsync
+	       ----  ----    ----  -----  -----  -----    -----    -----
       80x25     720   400      27     45     35     12      108        2
       80x30     720   480      27     45     30      9      108        2
 
@@ -297,8 +297,8 @@
 
    As a comparison, graphics/monitor.h suggests the following:
 
-               xres  yres    left  right  upper  lower    hsync    vsync
-               ----  ----    ----  -----  -----  -----    -----    -----
+	       xres  yres    left  right  upper  lower    hsync    vsync
+	       ----  ----    ----  -----  -----  -----    -----    -----
 
       VGA       640   480      52    112     24     19    112 -      2 +
       VGA70     640   400      52    112     27     21    112 -      2 -
@@ -309,10 +309,10 @@
 
       VSYNC    HSYNC    Vertical size    Vertical total
       -----    -----    -------------    --------------
-        +        +           Reserved          Reserved
-        +        -                400               414
-        -        +                350               362
-        -        -                480               496
+	+        +           Reserved          Reserved
+	+        -                400               414
+	-        +                350               362
+	-        -                480               496
 
    Source: CL-GD542X Technical Reference Manual, Cirrus Logic, Oct 1992
 
@@ -326,33 +326,34 @@
    -----------
 
       - a scanline is 64 µs long, of which 52.48 µs are visible. This is about
-        736 visible 70 ns pixels per line.
+	736 visible 70 ns pixels per line.
       - we have 625 scanlines, of which 575 are visible (interlaced); after
-        rounding this becomes 576.
+	rounding this becomes 576.
 
    RETMA -> NTSC
    -------------
 
       - a scanline is 63.5 µs long, of which 53.5 µs are visible.  This is about
-        736 visible 70 ns pixels per line.
+	736 visible 70 ns pixels per line.
       - we have 525 scanlines, of which 485 are visible (interlaced); after
-        rounding this becomes 484.
+	rounding this becomes 484.
 
    Thus if you want a PAL compatible display, you have to do the following:
 
       - set the FB_SYNC_BROADCAST flag to indicate that standard broadcast
-        timings are to be used.
-      - make sure upper_margin+yres+lower_margin+vsync_len = 625 for an
-        interlaced, 312 for a non-interlaced and 156 for a doublescanned
-        display.
-      - make sure left_margin+xres+right_margin+hsync_len = 1816 for a SHRES,
-        908 for a HIRES and 454 for a LORES display.
+	timings are to be used.
+      - make sure upper_margin + yres + lower_margin + vsync_len = 625 for an
+	interlaced, 312 for a non-interlaced and 156 for a doublescanned
+	display.
+      - make sure left_margin + xres + right_margin + hsync_len = 1816 for a
+	SHRES, 908 for a HIRES and 454 for a LORES display.
       - the left visible part begins at 360 (SHRES; HIRES:180, LORES:90),
-        left_margin+2*hsync_len must be greater or equal.
+	left_margin + 2 * hsync_len must be greater or equal.
       - the upper visible part begins at 48 (interlaced; non-interlaced:24,
-        doublescanned:12), upper_margin+2*vsync_len must be greater or equal.
+	doublescanned:12), upper_margin + 2 * vsync_len must be greater or
+	equal.
       - ami_encode_var() calculates margins with a hsync of 5320 ns and a vsync
-        of 4 scanlines
+	of 4 scanlines
 
    The settings for a NTSC compatible display are straightforward.
 
@@ -361,7 +362,7 @@
    anything about horizontal/vertical synchronizatio