Staging: sxg: clean up C99 comments

Change  C99 comments to C89 comments

Some nested comments seem to have been missed and some blocks are redundantly
commented, but at least most of the //'s are gone

Signed-off by: J.R. Mauro <jrm8005@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

2 files changed, 580 insertions, 580 deletions

diff --git a/drivers/staging/sxg/sxg.c b/drivers/staging/sxg/sxg.c
index d8772e5bf2d..3b05acf35d8 100644
--- a/drivers/staging/sxg/sxg.c
+++ b/drivers/staging/sxg/sxg.c
@@ -223,7 +223,7 @@ static void sxg_dbg_macaddrs(p_adapter_t adapter)
 	return;
 }
 
-// SXG Globals
+/* SXG Globals */
 static SXG_DRIVER SxgDriver;
 
 #ifdef  ATKDBG
@@ -250,7 +250,7 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 	u32 ThisSectionSize;
 	u32 *Instruction = NULL;
 	u32 BaseAddress, AddressOffset, Address;
-//      u32                         Failure;
+/*      u32                         Failure; */
 	u32 ValueRead;
 	u32 i;
 	u32 numSections = 0;
@@ -262,7 +262,7 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 	DBG_ERROR("sxg: %s ENTER\n", __func__);
 
 	switch (UcodeSel) {
-	case SXG_UCODE_SAHARA:	// Sahara operational ucode
+	case SXG_UCODE_SAHARA:	/* Sahara operational ucode */
 		numSections = SNumSections;
 		for (i = 0; i < numSections; i++) {
 			sectionSize[i] = SSectionSize[i];
@@ -276,13 +276,13 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 	}
 
 	DBG_ERROR("sxg: RESET THE CARD\n");
-	// First, reset the card
+	/* First, reset the card */
 	WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
 
-	// Download each section of the microcode as specified in
-	// its download file.  The *download.c file is generated using
-	// the saharaobjtoc facility which converts the metastep .obj
-	// file to a .c file which contains a two dimentional array.
+	/* Download each section of the microcode as specified in */
+	/* its download file.  The *download.c file is generated using */
+	/* the saharaobjtoc facility which converts the metastep .obj */
+	/* file to a .c file which contains a two dimentional array. */
 	for (Section = 0; Section < numSections; Section++) {
 		DBG_ERROR("sxg: SECTION # %d\n", Section);
 		switch (UcodeSel) {
@@ -294,35 +294,35 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 			break;
 		}
 		BaseAddress = sectionStart[Section];
-		ThisSectionSize = sectionSize[Section] / 12;	// Size in instructions
+		ThisSectionSize = sectionSize[Section] / 12;	/* Size in instructions */
 		for (AddressOffset = 0; AddressOffset < ThisSectionSize;
 		     AddressOffset++) {
 			Address = BaseAddress + AddressOffset;
 			ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
-			// Write instruction bits 31 - 0
+			/* Write instruction bits 31 - 0 */
 			WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
-			// Write instruction bits 63-32
+			/* Write instruction bits 63-32 */
 			WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
 				  FLUSH);
-			// Write instruction bits 95-64
+			/* Write instruction bits 95-64 */
 			WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
 				  FLUSH);
-			// Write instruction address with the WRITE bit set
+			/* Write instruction address with the WRITE bit set */
 			WRITE_REG(HwRegs->UcodeAddr,
 				  (Address | MICROCODE_ADDRESS_WRITE), FLUSH);
-			// Sahara bug in the ucode download logic - the write to DataLow
-			// for the next instruction could get corrupted.  To avoid this,
-			// write to DataLow again for this instruction (which may get
-			// corrupted, but it doesn't matter), then increment the address
-			// and write the data for the next instruction to DataLow.  That
-			// write should succeed.
+			/* Sahara bug in the ucode download logic - the write to DataLow */
+			/* for the next instruction could get corrupted.  To avoid this, */
+			/* write to DataLow again for this instruction (which may get */
+			/* corrupted, but it doesn't matter), then increment the address */
+			/* and write the data for the next instruction to DataLow.  That */
+			/* write should succeed. */
 			WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
-			// Advance 3 u32S to start of next instruction
+			/* Advance 3 u32S to start of next instruction */
 			Instruction += 3;
 		}
 	}
-	// Now repeat the entire operation reading the instruction back and
-	// checking for parity errors
+	/* Now repeat the entire operation reading the instruction back and */
+	/* checking for parity errors */
 	for (Section = 0; Section < numSections; Section++) {
 		DBG_ERROR("sxg: check SECTION # %d\n", Section);
 		switch (UcodeSel) {
@@ -334,51 +334,51 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 			break;
 		}
 		BaseAddress = sectionStart[Section];
-		ThisSectionSize = sectionSize[Section] / 12;	// Size in instructions
+		ThisSectionSize = sectionSize[Section] / 12;	/* Size in instructions */
 		for (AddressOffset = 0; AddressOffset < ThisSectionSize;
 		     AddressOffset++) {
 			Address = BaseAddress + AddressOffset;
-			// Write the address with the READ bit set
+			/* Write the address with the READ bit set */
 			WRITE_REG(HwRegs->UcodeAddr,
 				  (Address | MICROCODE_ADDRESS_READ), FLUSH);
-			// Read it back and check parity bit.
+			/* Read it back and check parity bit. */
 			READ_REG(HwRegs->UcodeAddr, ValueRead);
 			if (ValueRead & MICROCODE_ADDRESS_PARITY) {
 				DBG_ERROR("sxg: %s PARITY ERROR\n",
 					  __func__);
 
-				return (FALSE);	// Parity error
+				return (FALSE);	/* Parity error */
 			}
 			ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
-			// Read the instruction back and compare
+			/* Read the instruction back and compare */
 			READ_REG(HwRegs->UcodeDataLow, ValueRead);
 			if (ValueRead != *Instruction) {
 				DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
 					  __func__);
-				return (FALSE);	// Miscompare
+				return (FALSE);	/* Miscompare */
 			}
 			READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
 			if (ValueRead != *(Instruction + 1)) {
 				DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
 					  __func__);
-				return (FALSE);	// Miscompare
+				return (FALSE);	/* Miscompare */
 			}
 			READ_REG(HwRegs->UcodeDataHigh, ValueRead);
 			if (ValueRead != *(Instruction + 2)) {
 				DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
 					  __func__);
-				return (FALSE);	// Miscompare
+				return (FALSE);	/* Miscompare */
 			}
-			// Advance 3 u32S to start of next instruction
+			/* Advance 3 u32S to start of next instruction */
 			Instruction += 3;
 		}
 	}
 
-	// Everything OK, Go.
+	/* Everything OK, Go. */
 	WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
 
-	// Poll the CardUp register to wait for microcode to initialize
-	// Give up after 10,000 attemps (500ms).
+	/* Poll the CardUp register to wait for microcode to initialize */
+	/* Give up after 10,000 attemps (500ms). */
 	for (i = 0; i < 10000; i++) {
 		udelay(50);
 		READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
@@ -390,11 +390,11 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
 	if (i == 10000) {
 		DBG_ERROR("sxg: %s TIMEOUT\n", __func__);
 
-		return (FALSE);	// Timeout
+		return (FALSE);	/* Timeout */
 	}
-	// Now write the LoadSync register.  This is used to
-	// synchronize with the card so it can scribble on the memory
-	// that contained 0xCAFE from the "CardUp" step above
+	/* Now write the LoadSync register.  This is used to */
+	/* synchronize with the card so it can scribble on the memory */
+	/* that contained 0xCAFE from the "CardUp" step above */
 	if (UcodeSel == SXG_UCODE_SAHARA) {
 		WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
 	}
@@ -420,22 +420,22 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 	int status;
 	u32 i;
 	u32 RssIds, IsrCount;
-//      PSXG_XMT_RING                                   XmtRing;
-//      PSXG_RCV_RING                                   RcvRing;
+/*      PSXG_XMT_RING                                   XmtRing; */
+/*      PSXG_RCV_RING                                   RcvRing; */
 
 	DBG_ERROR("%s ENTER\n", __func__);
 
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
 		  adapter, 0, 0, 0);
 
-	// Windows tells us how many CPUs it plans to use for
-	// RSS
+	/* Windows tells us how many CPUs it plans to use for */
+	/* RSS */
 	RssIds = SXG_RSS_CPU_COUNT(adapter);
 	IsrCount = adapter->MsiEnabled ? RssIds : 1;
 
 	DBG_ERROR("%s Setup the spinlocks\n", __func__);
 
-	// Allocate spinlocks and initialize listheads first.
+	/* Allocate spinlocks and initialize listheads first. */
 	spin_lock_init(&adapter->RcvQLock);
 	spin_lock_init(&adapter->SglQLock);
 	spin_lock_init(&adapter->XmtZeroLock);
@@ -450,21 +450,21 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 	InitializeListHead(&adapter->FreeSglBuffers);
 	InitializeListHead(&adapter->AllSglBuffers);
 
-	// Mark these basic allocations done.  This flags essentially
-	// tells the SxgFreeResources routine that it can grab spinlocks
-	// and reference listheads.
+	/* Mark these basic allocations done.  This flags essentially */
+	/* tells the SxgFreeResources routine that it can grab spinlocks */
+	/* and reference listheads. */
 	adapter->BasicAllocations = TRUE;
-	// Main allocation loop.  Start with the maximum supported by
-	// the microcode and back off if memory allocation
-	// fails.  If we hit a minimum, fail.
+	/* Main allocation loop.  Start with the maximum supported by */
+	/* the microcode and back off if memory allocation */
+	/* fails.  If we hit a minimum, fail. */
 
 	for (;;) {
 		DBG_ERROR("%s Allocate XmtRings size[%lx]\n", __func__,
 			  (sizeof(SXG_XMT_RING) * 1));
 
-		// Start with big items first - receive and transmit rings.  At the moment
-		// I'm going to keep the ring size fixed and adjust the number of
-		// TCBs if we fail.  Later we might consider reducing the ring size as well..
+		/* Start with big items first - receive and transmit rings.  At the moment */
+		/* I'm going to keep the ring size fixed and adjust the number of */
+		/* TCBs if we fail.  Later we might consider reducing the ring size as well.. */
 		adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
 							 sizeof(SXG_XMT_RING) *
 							 1,
@@ -490,7 +490,7 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 		break;
 
 	      per_tcb_allocation_failed:
-		// an allocation failed.  Free any successful allocations.
+		/* an allocation failed.  Free any successful allocations. */
 		if (adapter->XmtRings) {
 			pci_free_consistent(adapter->pcidev,
 					    sizeof(SXG_XMT_RING) * 4096,
@@ -505,22 +505,22 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 					    adapter->PRcvRings);
 			adapter->RcvRings = NULL;
 		}
-		// Loop around and try again....
+		/* Loop around and try again.... */
 	}
 
 	DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__);
-	// Initialize rcv zero and xmt zero rings
+	/* Initialize rcv zero and xmt zero rings */
 	SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
 	SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
 
-	// Sanity check receive data structure format
+	/* Sanity check receive data structure format */
 	ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
 	       (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
 	ASSERT(sizeof(SXG_RCV_DESCRIPTOR_BLOCK) ==
 	       SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
 
-	// Allocate receive data buffers.  We allocate a block of buffers and
-	// a corresponding descriptor block at once.  See sxghw.h:SXG_RCV_BLOCK
+	/* Allocate receive data buffers.  We allocate a block of buffers and */
+	/* a corresponding descriptor block at once.  See sxghw.h:SXG_RCV_BLOCK */
 	for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
 	     i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
 		sxg_allocate_buffer_memory(adapter,
@@ -528,8 +528,8 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 							      ReceiveBufferSize),
 					   SXG_BUFFER_TYPE_RCV);
 	}
-	// NBL resource allocation can fail in the 'AllocateComplete' routine, which
-	// doesn't return status.  Make sure we got the number of buffers we requested
+	/* NBL resource allocation can fail in the 'AllocateComplete' routine, which */
+	/* doesn't return status.  Make sure we got the number of buffers we requested */
 	if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
 			  adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
@@ -540,14 +540,14 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 	DBG_ERROR("%s Allocate EventRings size[%lx]\n", __func__,
 		  (sizeof(SXG_EVENT_RING) * RssIds));
 
-	// Allocate event queues.
+	/* Allocate event queues. */
 	adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
 						   sizeof(SXG_EVENT_RING) *
 						   RssIds,
 						   &adapter->PEventRings);
 
 	if (!adapter->EventRings) {
-		// Caller will call SxgFreeAdapter to clean up above allocations
+		/* Caller will call SxgFreeAdapter to clean up above allocations */
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
 			  adapter, SXG_MAX_ENTRIES, 0, 0);
 		status = STATUS_RESOURCES;
@@ -556,11 +556,11 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 	memset(adapter->EventRings, 0, sizeof(SXG_EVENT_RING) * RssIds);
 
 	DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount);
-	// Allocate ISR
+	/* Allocate ISR */
 	adapter->Isr = pci_alloc_consistent(adapter->pcidev,
 					    IsrCount, &adapter->PIsr);
 	if (!adapter->Isr) {
-		// Caller will call SxgFreeAdapter to clean up above allocations
+		/* Caller will call SxgFreeAdapter to clean up above allocations */
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
 			  adapter, SXG_MAX_ENTRIES, 0, 0);
 		status = STATUS_RESOURCES;
@@ -571,7 +571,7 @@ static int sxg_allocate_resources(p_adapter_t adapter)
 	DBG_ERROR("%s Allocate shared XMT ring zero index location size[%lx]\n",
 		  __func__, sizeof(u32));
 
-	// Allocate shared XMT ring zero index location
+	/* Allocate shared XMT ring zero index location */
 	adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
 							 sizeof(u32),
 							 &adapter->
@@ -607,13 +607,13 @@ static void sxg_config_pci(struct pci_dev *pcidev)
 
 	pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
 	DBG_ERROR("sxg: %s  PCI command[%4.4x]\n", __func__, pci_command);
-	// Set the command register
-	new_command = pci_command | (PCI_COMMAND_MEMORY |	// Memory Space Enable
-				     PCI_COMMAND_MASTER |	// Bus master enable
-				     PCI_COMMAND_INVALIDATE |	// Memory write and invalidate
-				     PCI_COMMAND_PARITY |	// Parity error response
-				     PCI_COMMAND_SERR |	// System ERR
-				     PCI_COMMAND_FAST_BACK);	// Fast back-to-back
+	/* Set the command register */
+	new_command = pci_command | (PCI_COMMAND_MEMORY |	/* Memory Space Enable */
+				     PCI_COMMAND_MASTER |	/* Bus master enable */
+				     PCI_COMMAND_INVALIDATE |	/* Memory write and invalidate */
+				     PCI_COMMAND_PARITY |	/* Parity error response */
+				     PCI_COMMAND_SERR |	/* System ERR */
+				     PCI_COMMAND_FAST_BACK);	/* Fast back-to-back */
 	if (pci_command != new_command) {
 		DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
 			  __func__, pci_command, new_command);
@@ -636,7 +636,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 	DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
 		  __func__, jiffies, smp_processor_id());
 
-	// Initialize trace buffer
+	/* Initialize trace buffer */
 #ifdef ATKDBG
 	SxgTraceBuffer = &LSxgTraceBuffer;
 	SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
@@ -738,13 +738,13 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 	adapter->UcodeRegs = (void *)memmapped_ioaddr;
 
 	adapter->State = SXG_STATE_INITIALIZING;
-	// Maintain a list of all adapters anchored by
-	// the global SxgDriver structure.
+	/* Maintain a list of all adapters anchored by */
+	/* the global SxgDriver structure. */
 	adapter->Next = SxgDriver.Adapters;
 	SxgDriver.Adapters = adapter;
 	adapter->AdapterID = ++SxgDriver.AdapterID;
 
-	// Initialize CRC table used to determine multicast hash
+	/* Initialize CRC table used to determine multicast hash */
 	sxg_mcast_init_crc32();
 
 	adapter->JumboEnabled = FALSE;
@@ -757,10 +757,10 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 		adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
 	}
 
-//    status = SXG_READ_EEPROM(adapter);
-//    if (!status) {
-//        goto sxg_init_bad;
-//    }
+/*    status = SXG_READ_EEPROM(adapter); */
+/*    if (!status) { */
+/*        goto sxg_init_bad; */
+/*    } */
 
 	DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__);
 	sxg_config_pci(pcidev);
@@ -780,11 +780,11 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 	adapter->irq = pcidev->irq;
 	adapter->next_netdevice = head_netdevice;
 	head_netdevice = netdev;
-//      adapter->chipid = chip_idx;
-	adapter->port = 0;	//adapter->functionnumber;
+/*      adapter->chipid = chip_idx; */
+	adapter->port = 0;	/*adapter->functionnumber; */
 	adapter->cardindex = adapter->port;
 
-	// Allocate memory and other resources
+	/* Allocate memory and other resources */
 	DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__);
 	status = sxg_allocate_resources(adapter);
 	DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
@@ -819,7 +819,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 #endif
 
 	strcpy(netdev->name, "eth%d");
-//  strcpy(netdev->name, pci_name(pcidev));
+/*  strcpy(netdev->name, pci_name(pcidev)); */
 	if ((err = register_netdev(netdev))) {
 		DBG_ERROR("Cannot register net device, aborting. %s\n",
 			  netdev->name);
@@ -832,9 +832,9 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
 	     netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
 	     netdev->dev_addr[4], netdev->dev_addr[5]);
 
-//sxg_init_bad:
+/*sxg_init_bad: */
 	ASSERT(status == FALSE);
-//      sxg_free_adapter(adapter);
+/*      sxg_free_adapter(adapter); */
 
 	DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__,
 		  status, jiffies, smp_processor_id());
@@ -874,12 +874,12 @@ static void sxg_disable_interrupt(p_adapter_t adapter)
 {
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
 		  adapter, adapter->InterruptsEnabled, 0, 0);
-	// For now, RSS is disabled with line based interrupts
+	/* For now, RSS is disabled with line based interrupts */
 	ASSERT(adapter->RssEnabled == FALSE);
 	ASSERT(adapter->MsiEnabled == FALSE);
-	//
-	// Turn off interrupts by writing to the icr register.
-	//
+	/* */
+	/* Turn off interrupts by writing to the icr register. */
+	/* */
 	WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
 
 	adapter->InterruptsEnabled = 0;
@@ -905,12 +905,12 @@ static void sxg_enable_interrupt(p_adapter_t adapter)
 {
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
 		  adapter, adapter->InterruptsEnabled, 0, 0);
-	// For now, RSS is disabled with line based interrupts
+	/* For now, RSS is disabled with line based interrupts */
 	ASSERT(adapter->RssEnabled == FALSE);
 	ASSERT(adapter->MsiEnabled == FALSE);
-	//
-	// Turn on interrupts by writing to the icr register.
-	//
+	/* */
+	/* Turn on interrupts by writing to the icr register. */
+	/* */
 	WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
 
 	adapter->InterruptsEnabled = 1;
@@ -935,29 +935,29 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
 {
 	p_net_device dev = (p_net_device) dev_id;
 	p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
-//      u32                 CpuMask = 0, i;
+/*      u32                 CpuMask = 0, i; */
 
 	adapter->Stats.NumInts++;
 	if (adapter->Isr[0] == 0) {
-		// The SLIC driver used to experience a number of spurious interrupts
-		// due to the delay associated with the masking of the interrupt
-		// (we'd bounce back in here).  If we see that again with Sahara,
-		// add a READ_REG of the Icr register after the WRITE_REG below.
+		/* The SLIC driver used to experience a number of spurious interrupts */
+		/* due to the delay associated with the masking of the interrupt */
+		/* (we'd bounce back in here).  If we see that again with Sahara, */
+		/* add a READ_REG of the Icr register after the WRITE_REG below. */
 		adapter->Stats.FalseInts++;
 		return IRQ_NONE;
 	}
-	//
-	// Move the Isr contents and clear the value in
-	// shared memory, and mask interrupts
-	//
+	/* */
+	/* Move the Isr contents and clear the value in */
+	/* shared memory, and mask interrupts */
+	/* */
 	adapter->IsrCopy[0] = adapter->Isr[0];
 	adapter->Isr[0] = 0;
 	WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
-//      ASSERT(adapter->IsrDpcsPending == 0);
-#if XXXTODO			// RSS Stuff
-	// If RSS is enabled and the ISR specifies
-	// SXG_ISR_EVENT, then schedule DPC's
-	// based on event queues.
+/*      ASSERT(adapter->IsrDpcsPending == 0); */
+#if XXXTODO			/* RSS Stuff */
+	/* If RSS is enabled and the ISR specifies */
+	/* SXG_ISR_EVENT, then schedule DPC's */
+	/* based on event queues. */
 	if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
 		for (i = 0;
 		     i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
@@ -973,8 +973,8 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
 			}
 		}
 	}
-	// Now, either schedule the CPUs specified by the CpuMask,
-	// or queue default
+	/* Now, either schedule the CPUs specified by the CpuMask, */
+	/* or queue default */
 	if (CpuMask) {
 		*QueueDefault = FALSE;
 	} else {
@@ -983,9 +983,9 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
 	}
 	*TargetCpus = CpuMask;
 #endif
-	//
-	//  There are no DPCs in Linux, so call the handler now
-	//
+	/* */
+	/*  There are no DPCs in Linux, so call the handler now */
+	/* */
 	sxg_handle_interrupt(adapter);
 
 	return IRQ_HANDLED;
@@ -993,7 +993,7 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
 
 static void sxg_handle_interrupt(p_adapter_t adapter)
 {
-//    unsigned char           RssId   = 0;
+/*    unsigned char           RssId   = 0; */
 	u32 NewIsr;
 
 	if (adapter->Stats.RcvNoBuffer < 5) {
@@ -1002,32 +1002,32 @@ static void sxg_handle_interrupt(p_adapter_t adapter)
 	}
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
 		  adapter, adapter->IsrCopy[0], 0, 0);
-	// For now, RSS is disabled with line based interrupts
+	/* For now, RSS is disabled with line based interrupts */
 	ASSERT(adapter->RssEnabled == FALSE);
 	ASSERT(adapter->MsiEnabled == FALSE);
 	ASSERT(adapter->IsrCopy[0]);
-/////////////////////////////
+/*/////////////////////////// */
 
-	// Always process the event queue.
+	/* Always process the event queue. */
 	sxg_process_event_queue(adapter,
 				(adapter->RssEnabled ? /*RssId */ 0 : 0));
 
-#if XXXTODO			// RSS stuff
+#if XXXTODO			/* RSS stuff */
 	if (--adapter->IsrDpcsPending) {
-		// We're done.
+		/* We're done. */
 		ASSERT(adapter->RssEnabled);
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
 			  adapter, 0, 0, 0);
 		return;
 	}
 #endif
-	//
-	// Last (or only) DPC processes the ISR and clears the interrupt.
-	//
+	/* */
+	/* Last (or only) DPC processes the ISR and clears the interrupt. */
+	/* */
 	NewIsr = sxg_process_isr(adapter, 0);
-	//
-	// Reenable interrupts
-	//
+	/* */
+	/* Reenable interrupts */
+	/* */
 	adapter->IsrCopy[0] = 0;
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
 		  adapter, NewIsr, 0, 0);
@@ -1063,29 +1063,29 @@ static int sxg_process_isr(p_adapter_t adapter, u32 MessageId)
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
 		  adapter, Isr, 0, 0);
 
-	// Error
+	/* Error */
 	if (Isr & SXG_ISR_ERR) {
 		if (Isr & SXG_ISR_PDQF) {
 			adapter->Stats.PdqFull++;
 			DBG_ERROR("%s: SXG_ISR_ERR  PDQF!!\n", __func__);
 		}
-		// No host buffer
+		/* No host buffer */
 		if (Isr & SXG_ISR_RMISS) {
-			// There is a bunch of code in the SLIC driver which
-			// attempts to process more receive events per DPC
-			// if we start to fall behind.  We'll probably
-			// need to do something similar here, but hold
-			// off for now.  I don't want to make the code more
-			// complicated than strictly needed.
+			/* There is a bunch of code in the SLIC driver which */
+			/* attempts to process more receive events per DPC */
+			/* if we start to fall behind.  We'll probably */
+			/* need to do something similar here, but hold */
+			/* off for now.  I don't want to make the code more */
+			/* complicated than strictly needed. */
 			adapter->Stats.RcvNoBuffer++;
 			if (adapter->Stats.RcvNoBuffer < 5) {
 				DBG_ERROR("%s: SXG_ISR_ERR  RMISS!!\n",
 					  __func__);
 			}
 		}
-		// Card crash
+		/* Card crash */
 		if (Isr & SXG_ISR_DEAD) {
-			// Set aside the crash info and set the adapter state to RESET
+			/* Set aside the crash info and set the adapter state to RESET */
 			adapter->CrashCpu =
 			    (unsigned char)((Isr & SXG_ISR_CPU) >>
 					    SXG_ISR_CPU_SHIFT);
@@ -1094,44 +1094,44 @@ static int sxg_process_isr(p_adapter_t adapter, u32 MessageId)
 			DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__,
 				  adapter->CrashLocation, adapter->CrashCpu);
 		}
-		// Event ring full
+		/* Event ring full */
 		if (Isr & SXG_ISR_ERFULL) {
-			// Same issue as RMISS, really.  This means the
-			// host is falling behind the card.  Need to increase
-			// event ring size, process more events per interrupt,
-			// and/or reduce/remove interrupt aggregation.
+			/* Same issue as RMISS, really.  This means the */
+			/* host is falling behind the card.  Need to increase */
+			/* event ring size, process more events per interrupt, */
+			/* and/or reduce/remove interrupt aggregation. */
 			adapter->Stats.EventRingFull++;
 			DBG_ERROR("%s: SXG_ISR_ERR  EVENT RING FULL!!\n",
 				  __func__);
 		}
-		// Transmit drop - no DRAM buffers or XMT error
+		/* Transmit drop - no DRAM buffers or XMT error */
 		if (Isr & SXG_ISR_XDROP) {
 			adapter->Stats.XmtDrops++;
 			adapter->Stats.XmtErrors++;
 			DBG_ERROR("%s: SXG_ISR_ERR  XDROP!!\n", __func__);
 		}
 	}
-	// Slowpath send completions
+	/* Slowpath send completions */
 	if (Isr & SXG_ISR_SPSEND) {
 		sxg_complete_slow_send(adapter);
 	}
-	// Dump
+	/* Dump */
 	if (Isr & SXG_ISR_UPC) {
-		ASSERT(adapter->DumpCmdRunning);	// Maybe change when debug is added..
+		ASSERT(adapter->DumpCmdRunning);	/* Maybe change when debug is added.. */
 		adapter->DumpCmdRunning = FALSE;
 	}
-	// Link event
+	/* Link event */
 	if (Isr & SXG_ISR_LINK) {
 		sxg_link_event(adapter);
 	}
-	// Debug - breakpoint hit
+	/* Debug - breakpoint hit */
 	if (Isr & SXG_ISR_BREAK) {
-		// At the moment AGDB isn't written to support interactive
-		// debug sessions.  When it is, this interrupt will be used
-		// to signal AGDB that it has hit a breakpoint.  For now, ASSERT.
+		/* At the moment AGDB isn't written to support interactive */
+		/* debug sessions.  When it is, this interrupt will be used */
+		/* to signal AGDB that it has hit a breakpoint.  For now, ASSERT. */
 		ASSERT(0);
 	}
-	// Heartbeat response
+	/* Heartbeat response */
 	if (Isr & SXG_ISR_PING) {
 		adapter->PingOutstanding = FALSE;
 	}
@@ -1171,39 +1171,39 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
 	       (adapter->State == SXG_STATE_PAUSING) ||
 	       (adapter->State == SXG_STATE_PAUSED) ||
 	       (adapter->State == SXG_STATE_HALTING));
-	// We may still have unprocessed events on the queue if
-	// the card crashed.  Don't process them.
+	/* We may still have unprocessed events on the queue if */
+	/* the card crashed.  Don't process them. */
 	if (adapter->Dead) {
 		return (0);
 	}
-	// In theory there should only be a single processor that
-	// accesses this queue, and only at interrupt-DPC time.  So
-	// we shouldn't need a lock for any of this.
+	/* In theory there should only be a single processor that */
+	/* accesses this queue, and only at interrupt-DPC time.  So */
+	/* we shouldn't need a lock for any of this. */
 	while (Event->Status & EVENT_STATUS_VALID) {
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
 			  Event, Event->Code, Event->Status,
 			  adapter->NextEvent);
 		switch (Event->Code) {
 		case EVENT_CODE_BUFFERS:
-			ASSERT(!(Event->CommandIndex & 0xFF00));	// SXG_RING_INFO Head & Tail == unsigned char
-			//
+			ASSERT(!(Event->CommandIndex & 0xFF00));	/* SXG_RING_INFO Head & Tail == unsigned char */
+			/* */
 			sxg_complete_descriptor_blocks(adapter,
 						       Event->CommandIndex);
-			//
+			/* */
 			break;
 		case EVENT_CODE_SLOWRCV:
 			--adapter->RcvBuffersOnCard;
 			if ((skb = sxg_slow_receive(adapter, Event))) {
 				u32 rx_bytes;
 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
-				// Add it to our indication list
+				/* Add it to our indication list */
 				SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
 						   IndicationList, num_skbs);
-				//  In Linux, we just pass up each skb to the protocol above at this point,
-				//  there is no capability of an indication list.
+				/*  In Linux, we just pass up each skb to the protocol above at this point, */
+				/*  there is no capability of an indication list. */
 #else
-// CHECK            skb_pull(skb, INIC_RCVBUF_HEADSIZE);
-				rx_bytes = Event->Length;	// (rcvbuf->length & IRHDDR_FLEN_MSK);
+/* CHECK            skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
+				rx_bytes = Event->Length;	/* (rcvbuf->length & IRHDDR_FLEN_MSK); */
 				skb_put(skb, rx_bytes);
 				adapter->stats.rx_packets++;
 				adapter->stats.rx_bytes += rx_bytes;
@@ -1219,42 +1219,42 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
 		default:
 			DBG_ERROR("%s: ERROR  Invalid EventCode %d\n",
 				  __func__, Event->Code);
-//                      ASSERT(0);
+/*                      ASSERT(0); */
 		}
-		// See if we need to restock card receive buffers.
-		// There are two things to note here:
-		//      First - This test is not SMP safe.  The
-		//              adapter->BuffersOnCard field is protected via atomic interlocked calls, but
-		//              we do not protect it with respect to these tests.  The only way to do that
-		//      is with a lock, and I don't want to grab a lock every time we adjust the
-		//      BuffersOnCard count.  Instead, we allow the buffer replenishment to be off
-		//      once in a while.  The worst that can happen is the card is given one
-		//      more-or-less descriptor block than the arbitrary value we've chosen.
-		//      No big deal
-		//      In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted.
-		//      Second - We expect this test to rarely evaluate to true.  We attempt to
-		//      refill descriptor blocks as they are returned to us
-		//      (sxg_complete_descriptor_blocks), so The only time this should evaluate
-		//      to true is when sxg_complete_descriptor_blocks failed to allocate
-		//              receive buffers.
+		/* See if we need to restock card receive buffers. */
+		/* There are two things to note here: */
+		/*      First - This test is not SMP safe.  The */
+		/*              adapter->BuffersOnCard field is protected via atomic interlocked calls, but */
+		/*              we do not protect it with respect to these tests.  The only way to do that */
+		/*      is with a lock, and I don't want to grab a lock every time we adjust the */
+		/*      BuffersOnCard count.  Instead, we allow the buffer replenishment to be off */
+		/*      once in a while.  The worst that can happen is the card is given one */
+		/*      more-or-less descriptor block than the arbitrary value we've chosen. */
+		/*      No big deal */
+		/*      In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. */
+		/*      Second - We expect this test to rarely evaluate to true.  We attempt to */
+		/*      refill descriptor blocks as they are returned to us */
+		/*      (sxg_complete_descriptor_blocks), so The only time this should evaluate */
+		/*      to true is when sxg_complete_descriptor_blocks failed to allocate */
+		/*              receive buffers. */
 		if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
 			sxg_stock_rcv_buffers(adapter);
 		}
-		// It's more efficient to just set this to zero.
-		// But clearing the top bit saves potential debug info...
+		/* It's more efficient to just set this to zero. */
+		/* But clearing the top bit saves potential debug info... */
 		Event->Status &= ~EVENT_STATUS_VALID;
-		// Advanct to the next event
+		/* Advanct to the next event */
 		SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
 		Event = &EventRing->Ring[adapter->NextEvent[RssId]];
 		EventsProcessed++;
 		if (EventsProcessed == EVENT_RING_BATCH) {
-			// Release a batch of events back to the card
+			/* Release a batch of events back to the card */
 			WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
 				  EVENT_RING_BATCH, FALSE);
 			EventsProcessed = 0;
-			// If we've processed our batch limit, break out of the
-			// loop and return SXG_ISR_EVENT to arrange for us to
-			// be called again
+			/* If we've processed our batch limit, break out of the */
+			/* loop and return SXG_ISR_EVENT to arrange for us to */
+			/* be called again */
 			if (Batches++ == EVENT_BATCH_LIMIT) {
 				SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
 					  TRACE_NOISY, "EvtLimit", Batches,
@@ -1265,14 +1265,14 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
 		}
 	}
 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
-	//
-	// Indicate any received dumb-nic frames
-	//
+	/* */
+	/* Indicate any received dumb-nic frames */
+	/* */
 	SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
 #endif
-	//
-	// Release events back to the card.
-	//
+	/* */
+	/* Release events back to the card. */
+	/* */
 	if (EventsProcessed) {
 		WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
 			  EventsProcessed, FALSE);
@@ -1299,43 +1299,43 @@ static void sxg_complete_slow_send(p_adapter_t adapter)
 	u32 *ContextType;
 	PSXG_CMD XmtCmd;
 
-	// NOTE - This lock is dropped and regrabbed in this loop.
-	// This means two different processors can both be running
-	// through this loop. Be *very* careful.
+	/* NOTE - This lock is dropped and regrabbed in this loop. */
+	/* This means two different processors can both be running */
+	/* through this loop. Be *very* careful. */
 	spin_lock(&adapter->XmtZeroLock);
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
 		  adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
 
 	while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) {
-		// Locate the current Cmd (ring descriptor entry), and
-		// associated SGL, and advance the tail
+		/* Locate the current Cmd (ring descriptor entry), and */
+		/* associated SGL, and advance the tail */
 		SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
 		ASSERT(ContextType);
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
 			  XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
-		// Clear the SGL field.
+		/* Clear the SGL field. */
 		XmtCmd->Sgl = 0;
 
 		switch (*ContextType) {
 		case SXG_SGL_DUMB:
 			{
 				struct sk_buff *skb;
-				// Dumb-nic send.  Command context is the dumb-nic SGL
+				/* Dumb-nic send.  Command context is the dumb-nic SGL */
 				skb = (struct sk_buff *)ContextType;
-				// Complete the send
+				/* Complete the send */
 				SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
 					  TRACE_IMPORTANT, "DmSndCmp", skb, 0,
 					  0, 0);
 				ASSERT(adapter->Stats.XmtQLen);
-				adapter->Stats.XmtQLen--;	// within XmtZeroLock
+				adapter->Stats.XmtQLen--;	/* within XmtZeroLock */
 				adapter->Stats.XmtOk++;
-				// Now drop the lock and complete the send back to
-				// Microsoft.  We need to drop the lock because
-				// Microsoft can come back with a chimney send, which
-				// results in a double trip in SxgTcpOuput
+				/* Now drop the lock and complete the send back to */
+				/* Microsoft.  We need to drop the lock because */
+				/* Microsoft can come back with a chimney send, which */
+				/* results in a double trip in SxgTcpOuput */
 				spin_unlock(&adapter->XmtZeroLock);
 				SXG_COMPLETE_DUMB_SEND(adapter, skb);
-				// and reacquire..
+				/* and reacquire.. */
 				spin_lock(&adapter->XmtZeroLock);
 			}
 			break;
@@ -1371,7 +1371,7 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
 	SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
 		  RcvDataBufferHdr, RcvDataBufferHdr->State,
 		  RcvDataBufferHdr->VirtualAddress);
-	// Drop rcv frames in non-running state
+	/* Drop rcv frames in non-running state */
 	switch (adapter->State) {
 	case SXG_STATE_RUNNING:
 		break;
@@ -1384,12 +1384,12 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
 		goto drop;
 	}
 
-	// Change buffer state to UPSTREAM
+	/* Change buffer state to UPSTREAM */
 	RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
 	if (Event->Status & EVENT_STATUS_RCVERR) {
 		SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
 			  Event, Event->Status, Event->HostHandle, 0);
-		// XXXTODO - Remove this print later
+		/* XXXTODO - Remove this print later */
 		DBG_ERROR("SXG: Receive error %x\n", *(u32 *)
 			  SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
 		sxg_process_rcv_error(adapter, *(u32 *)
@@ -1397,8 +1397,8 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
 				      (RcvDataBufferHdr));
 		goto drop;
 	}
-#if XXXTODO			// VLAN stuff
-	// If there's a VLAN tag, extract it and validate it
+#if XXXTODO			/* VLAN stuff */
+	/* If there's a VLAN tag, extract it and validate it