ibm_emac: Remove the ibm_emac driver

The arch/ppc sub-tree has been removed in the powerpc git tree.  The old
ibm_emac driver is no longer used by anything as a result of this.  This
removes it, leaving the ibm_newemac driver as the proper driver to use for
PowerPC boards with the EMAC hardware.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

19 files changed, 0 insertions, 5281 deletions

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 20b5367f7e0..0e0f6696cca 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1255,7 +1255,6 @@ config IBMVETH
 	  To compile this driver as a module, choose M here. The module will
 	  be called ibmveth.
 
-source "drivers/net/ibm_emac/Kconfig"
 source "drivers/net/ibm_newemac/Kconfig"
 
 config NET_PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index c96fe203680..c9faa460590 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -4,7 +4,6 @@
 
 obj-$(CONFIG_E1000) += e1000/
 obj-$(CONFIG_E1000E) += e1000e/
-obj-$(CONFIG_IBM_EMAC) += ibm_emac/
 obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/
 obj-$(CONFIG_IGB) += igb/
 obj-$(CONFIG_IXGBE) += ixgbe/
diff --git a/drivers/net/ibm_emac/Kconfig b/drivers/net/ibm_emac/Kconfig
deleted file mode 100644
index f61c48047dc..00000000000
--- a/drivers/net/ibm_emac/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-config IBM_EMAC
-	tristate "PowerPC 4xx on-chip Ethernet support"
-	depends on 4xx && !PPC_MERGE
-	help
-	  This driver supports the PowerPC 4xx EMAC family of on-chip
-          Ethernet controllers.
-
-config IBM_EMAC_RXB
-	int "Number of receive buffers"
-	depends on IBM_EMAC
-	default "128"
-
-config IBM_EMAC_TXB
-	int "Number of transmit buffers"
-	depends on IBM_EMAC
-	default "64"
-
-config IBM_EMAC_POLL_WEIGHT
-	int "MAL NAPI polling weight"
-	depends on IBM_EMAC
-	default "32"
-
-config IBM_EMAC_RX_COPY_THRESHOLD
-	int "RX skb copy threshold (bytes)"
-	depends on IBM_EMAC
-	default "256"
-
-config IBM_EMAC_RX_SKB_HEADROOM
-	int "Additional RX skb headroom (bytes)"
-	depends on IBM_EMAC
-	default "0"
-	help
-	  Additional receive skb headroom. Note, that driver
-	  will always reserve at least 2 bytes to make IP header
-	  aligned, so usually there is no need to add any additional
-	  headroom.
-
-	  If unsure, set to 0.
-
-config IBM_EMAC_PHY_RX_CLK_FIX
-	bool "PHY Rx clock workaround"
-	depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
-	help
-	  Enable this if EMAC attached to a PHY which doesn't generate
-	  RX clock if there is no link, if this is the case, you will
-	  see "TX disable timeout" or "RX disable timeout" in the system
-	  log.
-
-	  If unsure, say N.
-
-config IBM_EMAC_DEBUG
-	bool "Debugging"
-	depends on IBM_EMAC
-	default n
-
-config IBM_EMAC_ZMII
-	bool
-	depends on IBM_EMAC && (NP405H || NP405L || 44x)
-	default y
-
-config IBM_EMAC_RGMII
-	bool
-	depends on IBM_EMAC && 440GX
-	default y
-
-config IBM_EMAC_TAH
-	bool
-	depends on IBM_EMAC && 440GX
-	default y
-
diff --git a/drivers/net/ibm_emac/Makefile b/drivers/net/ibm_emac/Makefile
deleted file mode 100644
index f98ddf0e807..00000000000
--- a/drivers/net/ibm_emac/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the PowerPC 4xx on-chip ethernet driver
-#
-
-obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
-
-ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o 
-ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o
-ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o
-ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o
-ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
deleted file mode 100644
index 97ed22bb432..00000000000
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * drivers/net/ibm_emac/ibm_emac.h
- *
- * Register definitions for PowerPC 4xx on-chip ethernet contoller
- *
- * Copyright (c) 2004, 2005 Zultys Technologies.
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- *
- * Based on original work by
- *      Matt Porter <mporter@kernel.crashing.org>
- *      Armin Kuster <akuster@mvista.com>
- * 	Copyright 2002-2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#ifndef __IBM_EMAC_H_
-#define __IBM_EMAC_H_
-
-#include <linux/types.h>
-
-/* This is a simple check to prevent use of this driver on non-tested SoCs */
-#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
-    !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
-    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
-    !defined(CONFIG_440GR)
-#error	"Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
-#endif
-
-/* EMAC registers 		Write Access rules */
-struct emac_regs {
-	u32 mr0;		/* special 	*/
-	u32 mr1;		/* Reset 	*/
-	u32 tmr0;		/* special 	*/
-	u32 tmr1;		/* special 	*/
-	u32 rmr;		/* Reset 	*/
-	u32 isr;		/* Always 	*/
-	u32 iser;		/* Reset 	*/
-	u32 iahr;		/* Reset, R, T 	*/
-	u32 ialr;		/* Reset, R, T 	*/
-	u32 vtpid;		/* Reset, R, T 	*/
-	u32 vtci;		/* Reset, R, T 	*/
-	u32 ptr;		/* Reset,    T 	*/
-	u32 iaht1;		/* Reset, R	*/
-	u32 iaht2;		/* Reset, R	*/
-	u32 iaht3;		/* Reset, R	*/
-	u32 iaht4;		/* Reset, R	*/
-	u32 gaht1;		/* Reset, R	*/
-	u32 gaht2;		/* Reset, R	*/
-	u32 gaht3;		/* Reset, R	*/
-	u32 gaht4;		/* Reset, R	*/
-	u32 lsah;
-	u32 lsal;
-	u32 ipgvr;		/* Reset,    T 	*/
-	u32 stacr;		/* special 	*/
-	u32 trtr;		/* special 	*/
-	u32 rwmr;		/* Reset 	*/
-	u32 octx;
-	u32 ocrx;
-	u32 ipcr;
-};
-
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_ETHTOOL_REGS_VER		0
-#define EMAC_ETHTOOL_REGS_SIZE		(sizeof(struct emac_regs) - sizeof(u32))
-#else
-#define EMAC_ETHTOOL_REGS_VER		1
-#define EMAC_ETHTOOL_REGS_SIZE		sizeof(struct emac_regs)
-#endif
-
-/* EMACx_MR0 */
-#define EMAC_MR0_RXI			0x80000000
-#define EMAC_MR0_TXI			0x40000000
-#define EMAC_MR0_SRST			0x20000000
-#define EMAC_MR0_TXE			0x10000000
-#define EMAC_MR0_RXE			0x08000000
-#define EMAC_MR0_WKE			0x04000000
-
-/* EMACx_MR1 */
-#define EMAC_MR1_FDE			0x80000000
-#define EMAC_MR1_ILE			0x40000000
-#define EMAC_MR1_VLE			0x20000000
-#define EMAC_MR1_EIFC			0x10000000
-#define EMAC_MR1_APP			0x08000000
-#define EMAC_MR1_IST			0x01000000
-
-#define EMAC_MR1_MF_MASK		0x00c00000
-#define EMAC_MR1_MF_10			0x00000000
-#define EMAC_MR1_MF_100			0x00400000
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_MR1_MF_1000		0x00000000
-#define EMAC_MR1_MF_1000GPCS		0x00000000
-#define EMAC_MR1_MF_IPPA(id)		0x00000000
-#else
-#define EMAC_MR1_MF_1000		0x00800000
-#define EMAC_MR1_MF_1000GPCS		0x00c00000
-#define EMAC_MR1_MF_IPPA(id)		(((id) & 0x1f) << 6)
-#endif
-
-#define EMAC_TX_FIFO_SIZE		2048
-
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_MR1_RFS_4K			0x00300000
-#define EMAC_MR1_RFS_16K		0x00000000
-#define EMAC_RX_FIFO_SIZE(gige)		4096
-#define EMAC_MR1_TFS_2K			0x00080000
-#define EMAC_MR1_TR0_MULT		0x00008000
-#define EMAC_MR1_JPSM			0x00000000
-#define EMAC_MR1_MWSW_001		0x00000000
-#define EMAC_MR1_BASE(opb)		(EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
-#else
-#define EMAC_MR1_RFS_4K			0x00180000
-#define EMAC_MR1_RFS_16K		0x00280000
-#define EMAC_RX_FIFO_SIZE(gige)		((gige) ? 16384 : 4096)
-#define EMAC_MR1_TFS_2K			0x00020000
-#define EMAC_MR1_TR			0x00008000
-#define EMAC_MR1_MWSW_001		0x00001000
-#define EMAC_MR1_JPSM			0x00000800
-#define EMAC_MR1_OBCI_MASK		0x00000038
-#define EMAC_MR1_OBCI_50		0x00000000
-#define EMAC_MR1_OBCI_66		0x00000008
-#define EMAC_MR1_OBCI_83		0x00000010
-#define EMAC_MR1_OBCI_100		0x00000018
-#define EMAC_MR1_OBCI_100P		0x00000020
-#define EMAC_MR1_OBCI(freq)		((freq) <= 50  ? EMAC_MR1_OBCI_50 : \
-					 (freq) <= 66  ? EMAC_MR1_OBCI_66 : \
-					 (freq) <= 83  ? EMAC_MR1_OBCI_83 : \
-					 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
-#define EMAC_MR1_BASE(opb)		(EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
-					 EMAC_MR1_OBCI(opb))
-#endif
-
-/* EMACx_TMR0 */
-#define EMAC_TMR0_GNP			0x80000000
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_TMR0_DEFAULT		0x00000000	
-#else
-#define EMAC_TMR0_TFAE_2_32		0x00000001
-#define EMAC_TMR0_TFAE_4_64		0x00000002
-#define EMAC_TMR0_TFAE_8_128		0x00000003
-#define EMAC_TMR0_TFAE_16_256		0x00000004
-#define EMAC_TMR0_TFAE_32_512		0x00000005
-#define EMAC_TMR0_TFAE_64_1024		0x00000006
-#define EMAC_TMR0_TFAE_128_2048		0x00000007
-#define EMAC_TMR0_DEFAULT		EMAC_TMR0_TFAE_2_32
-#endif
-#define EMAC_TMR0_XMIT			(EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
-
-/* EMACx_TMR1 */
-
-/* IBM manuals are not very clear here. 
- * This is my interpretation of how things are. --ebs
- */
-#if defined(CONFIG_40x)
-#define EMAC_FIFO_ENTRY_SIZE		8
-#define EMAC_MAL_BURST_SIZE		(16 * 4)
-#else
-#define EMAC_FIFO_ENTRY_SIZE		16
-#define EMAC_MAL_BURST_SIZE		(64 * 4)
-#endif
-
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_TMR1(l,h)			(((l) << 27) | (((h) & 0xff) << 16))
-#else
-#define EMAC_TMR1(l,h)			(((l) << 27) | (((h) & 0x3ff) << 14))
-#endif
-
-/* EMACx_RMR */
-#define EMAC_RMR_SP			0x80000000
-#define EMAC_RMR_SFCS			0x40000000
-#define EMAC_RMR_RRP			0x20000000
-#define EMAC_RMR_RFP			0x10000000
-#define EMAC_RMR_ROP			0x08000000
-#define EMAC_RMR_RPIR			0x04000000
-#define EMAC_RMR_PPP			0x02000000
-#define EMAC_RMR_PME			0x01000000
-#define EMAC_RMR_PMME			0x00800000
-#define EMAC_RMR_IAE			0x00400000
-#define EMAC_RMR_MIAE			0x00200000
-#define EMAC_RMR_BAE			0x00100000
-#define EMAC_RMR_MAE			0x00080000
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_RMR_BASE			0x00000000
-#else
-#define EMAC_RMR_RFAF_2_32		0x00000001
-#define EMAC_RMR_RFAF_4_64		0x00000002
-#define EMAC_RMR_RFAF_8_128		0x00000003
-#define EMAC_RMR_RFAF_16_256		0x00000004
-#define EMAC_RMR_RFAF_32_512		0x00000005
-#define EMAC_RMR_RFAF_64_1024		0x00000006
-#define EMAC_RMR_RFAF_128_2048		0x00000007
-#define EMAC_RMR_BASE			EMAC_RMR_RFAF_128_2048
-#endif
-
-/* EMACx_ISR & EMACx_ISER */
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_ISR_TXPE			0x00000000
-#define EMAC_ISR_RXPE			0x00000000
-#define EMAC_ISR_TXUE			0x00000000
-#define EMAC_ISR_RXOE			0x00000000
-#else
-#define EMAC_ISR_TXPE			0x20000000
-#define EMAC_ISR_RXPE			0x10000000
-#define EMAC_ISR_TXUE			0x08000000
-#define EMAC_ISR_RXOE			0x04000000
-#endif
-#define EMAC_ISR_OVR			0x02000000
-#define EMAC_ISR_PP			0x01000000
-#define EMAC_ISR_BP			0x00800000
-#define EMAC_ISR_RP			0x00400000
-#define EMAC_ISR_SE			0x00200000
-#define EMAC_ISR_ALE			0x00100000
-#define EMAC_ISR_BFCS			0x00080000
-#define EMAC_ISR_PTLE			0x00040000
-#define EMAC_ISR_ORE			0x00020000
-#define EMAC_ISR_IRE			0x00010000
-#define EMAC_ISR_SQE			0x00000080
-#define EMAC_ISR_TE			0x00000040
-#define EMAC_ISR_MOS			0x00000002
-#define EMAC_ISR_MOF			0x00000001
-
-/* EMACx_STACR */
-#define EMAC_STACR_PHYD_MASK		0xffff
-#define EMAC_STACR_PHYD_SHIFT		16
-#define EMAC_STACR_OC			0x00008000
-#define EMAC_STACR_PHYE			0x00004000
-#define EMAC_STACR_STAC_MASK		0x00003000
-#define EMAC_STACR_STAC_READ		0x00001000
-#define EMAC_STACR_STAC_WRITE		0x00002000
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_STACR_OPBC_MASK		0x00000C00
-#define EMAC_STACR_OPBC_50		0x00000000
-#define EMAC_STACR_OPBC_66		0x00000400
-#define EMAC_STACR_OPBC_83		0x00000800
-#define EMAC_STACR_OPBC_100		0x00000C00
-#define EMAC_STACR_OPBC(freq)		((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
-					 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
-					 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
-#define EMAC_STACR_BASE(opb)		EMAC_STACR_OPBC(opb)
-#else
-#define EMAC_STACR_BASE(opb)		0x00000000
-#endif
-#define EMAC_STACR_PCDA_MASK		0x1f
-#define EMAC_STACR_PCDA_SHIFT		5
-#define EMAC_STACR_PRA_MASK		0x1f
-
-/*
- * For the 440SPe, AMCC inexplicably changed the polarity of
- * the "operation complete" bit in the MII control register.
- */
-#if defined(CONFIG_440SPE)
-static inline int emac_phy_done(u32 stacr)
-{
-	return !(stacr & EMAC_STACR_OC);
-};
-#define EMAC_STACR_START 		EMAC_STACR_OC
-
-#else /* CONFIG_440SPE */
-static inline int emac_phy_done(u32 stacr)
-{
-	return stacr & EMAC_STACR_OC;
-};
-#define EMAC_STACR_START 		0
-#endif /* !CONFIG_440SPE */
-
-/* EMACx_TRTR */
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_TRTR_SHIFT			27
-#else
-#define EMAC_TRTR_SHIFT			24
-#endif
-#define EMAC_TRTR(size)			((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
-
-/* EMACx_RWMR */
-#if !defined(CONFIG_IBM_EMAC4)
-#define EMAC_RWMR(l,h)			(((l) << 23) | ( ((h) & 0x1ff) << 7))	
-#else
-#define EMAC_RWMR(l,h)			(((l) << 22) | ( ((h) & 0x3ff) << 6))	
-#endif
-
-/* EMAC specific TX descriptor control fields (write access) */
-#define EMAC_TX_CTRL_GFCS		0x0200
-#define EMAC_TX_CTRL_GP			0x0100
-#define EMAC_TX_CTRL_ISA		0x0080
-#define EMAC_TX_CTRL_RSA		0x0040
-#define EMAC_TX_CTRL_IVT		0x0020
-#define EMAC_TX_CTRL_RVT		0x0010
-#define EMAC_TX_CTRL_TAH_CSUM		0x000e
-
-/* EMAC specific TX descriptor status fields (read access) */
-#define EMAC_TX_ST_BFCS			0x0200
-#define EMAC_TX_ST_LCS			0x0080
-#define EMAC_TX_ST_ED			0x0040
-#define EMAC_TX_ST_EC			0x0020
-#define EMAC_TX_ST_LC			0x0010
-#define EMAC_TX_ST_MC			0x0008
-#define EMAC_TX_ST_SC			0x0004
-#define EMAC_TX_ST_UR			0x0002
-#define EMAC_TX_ST_SQE			0x0001
-#if !defined(CONFIG_IBM_EMAC_TAH)
-#define EMAC_IS_BAD_TX(v)		((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
-					 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
-					 EMAC_TX_ST_MC | EMAC_TX_ST_UR))
-#else
-#define EMAC_IS_BAD_TX(v)		((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
-					 EMAC_TX_ST_EC | EMAC_TX_ST_LC))
-#endif					 
-
-/* EMAC specific RX descriptor status fields (read access) */
-#define EMAC_RX_ST_OE			0x0200
-#define EMAC_RX_ST_PP			0x0100
-#define EMAC_RX_ST_BP			0x0080
-#define EMAC_RX_ST_RP			0x0040
-#define EMAC_RX_ST_SE			0x0020
-#define EMAC_RX_ST_AE			0x0010
-#define EMAC_RX_ST_BFCS			0x0008
-#define EMAC_RX_ST_PTL			0x0004
-#define EMAC_RX_ST_ORE			0x0002
-#define EMAC_RX_ST_IRE			0x0001
-#define EMAC_RX_TAH_BAD_CSUM		0x0003
-#define EMAC_BAD_RX_MASK		(EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
-					 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
-					 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
-					 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
-					 EMAC_RX_ST_IRE )
-#endif /* __IBM_EMAC_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
deleted file mode 100644
index 73664f226f3..00000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ /dev/null
@@ -1,2263 +0,0 @@
-/*
- * drivers/net/ibm_emac/ibm_emac_core.c
- *
- * Driver for PowerPC 4xx on-chip ethernet controller.
- *
- * Copyright (c) 2004, 2005 Zultys Technologies.
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- *
- * Based on original work by
- * 	Matt Porter <mporter@kernel.crashing.org>
- *	(c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *      Armin Kuster <akuster@mvista.com>
- * 	Johnnie Peters <jpeters@mvista.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/crc32.h>
-#include <linux/ethtool.h>
-#include <linux/mii.h>
-#include <linux/bitops.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-#include <asm/uaccess.h>
-#include <asm/ocp.h>
-
-#include "ibm_emac_core.h"
-#include "ibm_emac_debug.h"
-
-/*
- * Lack of dma_unmap_???? calls is intentional.
- *
- * API-correct usage requires additional support state information to be 
- * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
- * EMAC design (e.g. TX buffer passed from network stack can be split into
- * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
- * maintaining such information will add additional overhead.
- * Current DMA API implementation for 4xx processors only ensures cache coherency
- * and dma_unmap_???? routines are empty and are likely to stay this way.
- * I decided to omit dma_unmap_??? calls because I don't want to add additional
- * complexity just for the sake of following some abstract API, when it doesn't
- * add any real benefit to the driver. I understand that this decision maybe 
- * controversial, but I really tried to make code API-correct and efficient 
- * at the same time and didn't come up with code I liked :(.                --ebs
- */
-
-#define DRV_NAME        "emac"
-#define DRV_VERSION     "3.54"
-#define DRV_DESC        "PPC 4xx OCP EMAC driver"
-
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_AUTHOR
-    ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
-MODULE_LICENSE("GPL");
-
-/* minimum number of free TX descriptors required to wake up TX process */
-#define EMAC_TX_WAKEUP_THRESH		(NUM_TX_BUFF / 4)
-
-/* If packet size is less than this number, we allocate small skb and copy packet 
- * contents into it instead of just sending original big skb up
- */
-#define EMAC_RX_COPY_THRESH		CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
-
-/* Since multiple EMACs share MDIO lines in various ways, we need
- * to avoid re-using the same PHY ID in cases where the arch didn't
- * setup precise phy_map entries
- */
-static u32 busy_phy_map;
-
-#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
-    (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
-/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
- * with PHY RX clock problem.
- * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
- * also allows controlling each EMAC clock
- */
-static inline void EMAC_RX_CLK_TX(int idx)
-{
-	unsigned long flags;
-	local_irq_save(flags);
-
-#if defined(CONFIG_405EP)
-	mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
-#else /* CONFIG_440EP || CONFIG_440GR */
-	SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
-#endif
-
-	local_irq_restore(flags);
-}
-
-static inline void EMAC_RX_CLK_DEFAULT(int idx)
-{
-	unsigned long flags;
-	local_irq_save(flags);
-
-#if defined(CONFIG_405EP)
-	mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
-#else /* CONFIG_440EP */
-	SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~(0x08000000 >> idx));
-#endif
-
-	local_irq_restore(flags);
-}
-#else
-#define EMAC_RX_CLK_TX(idx)		((void)0)
-#define EMAC_RX_CLK_DEFAULT(idx)	((void)0)
-#endif
-
-#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && defined(CONFIG_440GX)
-/* We can switch Ethernet clock to the internal source through SDR0_MFR[ECS],
- * unfortunately this is less flexible than 440EP case, because it's a global 
- * setting for all EMACs, therefore we do this clock trick only during probe.
- */
-#define EMAC_CLK_INTERNAL		SDR_WRITE(DCRN_SDR_MFR, \
-					    SDR_READ(DCRN_SDR_MFR) | 0x08000000)
-#define EMAC_CLK_EXTERNAL		SDR_WRITE(DCRN_SDR_MFR, \
-					    SDR_READ(DCRN_SDR_MFR) & ~0x08000000)
-#else
-#define EMAC_CLK_INTERNAL		((void)0)
-#define EMAC_CLK_EXTERNAL		((void)0)
-#endif
-
-/* I don't want to litter system log with timeout errors 
- * when we have brain-damaged PHY.
- */
-static inline void emac_report_timeout_error(struct ocp_enet_private *dev,
-					     const char *error)
-{
-#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
-	DBG("%d: %s" NL, dev->def->index, error);
-#else
-	if (net_ratelimit())
-		printk(KERN_ERR "emac%d: %s\n", dev->def->index, error);
-#endif
-}
-
-/* PHY polling intervals */
-#define PHY_POLL_LINK_ON	HZ
-#define PHY_POLL_LINK_OFF	(HZ / 5)
-
-/* Graceful stop timeouts in us. 
- * We should allow up to 1 frame time (full-duplex, ignoring collisions) 
- */
-#define STOP_TIMEOUT_10		1230	
-#define STOP_TIMEOUT_100	124
-#define STOP_TIMEOUT_1000	13
-#define STOP_TIMEOUT_1000_JUMBO	73
-
-/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
-static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
-	"rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
-	"tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
-	"rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
-	"rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
-	"rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
-	"rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
-	"rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
-	"rx_bad_packet", "rx_runt_packet", "rx_short_event",
-	"rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
-	"rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
-	"tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
-	"tx_bd_excessive_collisions", "tx_bd_late_collision",
-	"tx_bd_multple_collisions", "tx_bd_single_collision",
-	"tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
-	"tx_errors"
-};
-
-static irqreturn_t emac_irq(int irq, void *dev_instance);
-static void emac_clean_tx_ring(struct ocp_enet_private *dev);
-
-static inline int emac_phy_supports_gige(int phy_mode)
-{
-	return  phy_mode == PHY_MODE_GMII ||
-		phy_mode == PHY_MODE_RGMII ||
-		phy_mode == PHY_MODE_TBI ||
-		phy_mode == PHY_MODE_RTBI;
-}
-
-static inline int emac_phy_gpcs(int phy_mode)
-{
-	return  phy_mode == PHY_MODE_TBI ||
-		phy_mode == PHY_MODE_RTBI;
-}
-
-static inline void emac_tx_enable(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	u32 r;
-
-	local_irq_save(flags);
-
-	DBG("%d: tx_enable" NL, dev->def->index);
-
-	r = in_be32(&p->mr0);
-	if (!(r & EMAC_MR0_TXE))
-		out_be32(&p->mr0, r | EMAC_MR0_TXE);
-	local_irq_restore(flags);
-}
-
-static void emac_tx_disable(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	u32 r;
-
-	local_irq_save(flags);
-
-	DBG("%d: tx_disable" NL, dev->def->index);
-
-	r = in_be32(&p->mr0);
-	if (r & EMAC_MR0_TXE) {
-		int n = dev->stop_timeout;
-		out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
-		while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
-			udelay(1);
-			--n;
-		}	
-		if (unlikely(!n))
-			emac_report_timeout_error(dev, "TX disable timeout");
-	}
-	local_irq_restore(flags);
-}
-
-static void emac_rx_enable(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	u32 r;
-
-	local_irq_save(flags);
-	if (unlikely(dev->commac.rx_stopped))
-		goto out;
-
-	DBG("%d: rx_enable" NL, dev->def->index);
-
-	r = in_be32(&p->mr0);
-	if (!(r & EMAC_MR0_RXE)) {
-		if (unlikely(!(r & EMAC_MR0_RXI))) {
-			/* Wait if previous async disable is still in progress */
-			int n = dev->stop_timeout;
-			while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
-				udelay(1);
-				--n;
-			}	
-			if (unlikely(!n))
-				emac_report_timeout_error(dev,
-							  "RX disable timeout");
-		}
-		out_be32(&p->mr0, r | EMAC_MR0_RXE);
-	}
-      out:
-	local_irq_restore(flags);
-}
-
-static void emac_rx_disable(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	u32 r;
-
-	local_irq_save(flags);
-
-	DBG("%d: rx_disable" NL, dev->def->index);
-
-	r = in_be32(&p->mr0);
-	if (r & EMAC_MR0_RXE) {
-		int n = dev->stop_timeout;
-		out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
-		while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
-			udelay(1);
-			--n;
-		}	
-		if (unlikely(!n))
-			emac_report_timeout_error(dev, "RX disable timeout");
-	}
-	local_irq_restore(flags);
-}
-
-static inline void emac_rx_disable_async(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	u32 r;
-
-	local_irq_save(flags);
-
-	DBG("%d: rx_disable_async" NL, dev->def->index);
-
-	r = in_be32(&p->mr0);
-	if (r & EMAC_MR0_RXE)
-		out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
-	local_irq_restore(flags);
-}
-
-static int emac_reset(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	unsigned long flags;
-	int n = 20;
-
-	DBG("%d: reset" NL, dev->def->index);
-
-	local_irq_save(flags);
-
-	if (!dev->reset_failed) {
-		/* 40x erratum suggests stopping RX channel before reset,
-		 * we stop TX as well
-		 */
-		emac_rx_disable(dev);
-		emac_tx_disable(dev);
-	}
-
-	out_be32(&p->mr0, EMAC_MR0_SRST);
-	while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
-		--n;
-	local_irq_restore(flags);
-
-	if (n) {
-		dev->reset_failed = 0;
-		return 0;
-	} else {
-		emac_report_timeout_error(dev, "reset timeout");
-		dev->reset_failed = 1;
-		return -ETIMEDOUT;
-	}
-}
-
-static void emac_hash_mc(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	u16 gaht[4] = { 0 };
-	struct dev_mc_list *dmi;
-
-	DBG("%d: hash_mc %d" NL, dev->def->index, dev->ndev->mc_count);
-
-	for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
-		int bit;
-		DECLARE_MAC_BUF(mac);
-		DBG2("%d: mc %s" NL,
-		     dev->def->index, print_mac(mac, dmi->dmi_addr));
-
-		bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
-		gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
-	}
-	out_be32(&p->gaht1, gaht[0]);
-	out_be32(&p->gaht2, gaht[1]);
-	out_be32(&p->gaht3, gaht[2]);
-	out_be32(&p->gaht4, gaht[3]);
-}
-
-static inline u32 emac_iff2rmr(struct net_device *ndev)
-{
-	u32 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE |
-	    EMAC_RMR_BASE;
-
-	if (ndev->flags & IFF_PROMISC)
-		r |= EMAC_RMR_PME;
-	else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
-		r |= EMAC_RMR_PMME;
-	else if (ndev->mc_count > 0)
-		r |= EMAC_RMR_MAE;
-
-	return r;
-}
-
-static inline int emac_opb_mhz(void)
-{
-	return (ocp_sys_info.opb_bus_freq + 500000) / 1000000;
-}
-
-/* BHs disabled */
-static int emac_configure(struct ocp_enet_private *dev)
-{
-	struct emac_regs __iomem *p = dev->emacp;
-	struct net_device *ndev = dev->ndev;
-	int gige;
-	u32 r;
-
-	DBG("%d: configure" NL, dev->def->index);
-
-	if (emac_reset(dev) < 0)
-		return -ETIMEDOUT;
-
-	tah_reset(dev->tah_dev);
-
-	/* Mode register */
-	r = EMAC_MR1_BASE(emac_opb_mhz()) | EMAC_MR1_VLE | EMAC_MR1_IST;
-	if (dev->phy.duplex == DUPLEX_FULL)
-		r |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
-	dev->stop_timeout = STOP_TIMEOUT_10;
-	switch (dev->phy.speed) {
-	case SPEED_1000:
-		if (emac_phy_gpcs(dev->phy.mode)) {
-			r |= EMAC_MR1_MF_1000GPCS |
-			    EMAC_MR1_MF_IPPA(dev->phy.address);
-
-			/* Put some arbitrary OUI, Manuf & Rev IDs so we can
-			 * identify this GPCS PHY later.
-			 */
-			out_be32(&p->ipcr, 0xdeadbeef);
-		} else
-			r |= EMAC_MR1_MF_1000;
-		r |= EMAC_MR1_RFS_16K;
-		gige = 1;
-
-		if (dev->ndev->mtu > ETH_DATA_LEN) {
-			r |= EMAC_MR1_JPSM;
-			dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
-		} else
-			dev->stop_timeout = STOP_TIMEOUT_1000;
-		break;
-	case SPEED_100:
-		r |= EMAC_MR1_MF_100;
-		dev->stop_timeout = STOP_TIMEOUT_100;
-		/* Fall through */
-	default:
-		r |= EMAC_MR1_RFS_4K;
-		gige = 0;
-		break;
-	}
-
-	if (dev->rgmii_dev)
-		rgmii_set_speed(dev->rgmii_dev, dev->rgmii_input,
-				dev->phy.speed);
-	else
-		zmii_set_speed(dev->zmii_dev, dev->zmii_input, dev->phy.speed);
-
-#if !defined(CONFIG_40x)
-	/* on 40x erratum forces us to NOT use integrated flow control, 
-	 * let's hope it works on 44x ;)
-	 */
-	if (dev->phy.duplex == DUPLEX_FULL) {
-		if (dev->phy.pause)
-			r |= EMAC_MR1_EIFC | EMAC_MR1_APP;
-		else if (dev->phy.asym_pause)
-			r |= EMAC_MR1_APP;
-	}
-#endif
-	out_be32(&p->mr1, r);
-
-	/* Set individual MAC address */
-	out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
-	out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
-		 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
-		 ndev->dev_addr[5]);
-
-	/* VLAN Tag Protocol ID */
-	out_be32(&p->vtpid, 0x8100);
-
-	/* Receive mode register */
-	r = emac_iff2rmr(ndev);
-	if (r & EMAC_RMR_MAE)
-		emac_hash_mc(dev);
-	out_be32(&p->rmr, r);
-
-	/* FIFOs thresholds */
-	r = EMAC_TMR1((EMAC_MAL_BURST_SIZE / EMAC_FIFO_ENTRY_SIZE) + 1,
-		      EMAC_TX_FIFO_SIZE / 2 / EMAC_FIFO_ENTRY_SIZE);
-	out_be32(&p->tmr1, r);
-	out_be32(&p->trtr, EMAC_TRTR(EMAC_TX_FIFO_SIZE / 2));
-
-	/* PAUSE frame is sent when RX FIFO reaches its high-water mark,
-	   there should be still enough space in FIFO to allow the our link
-	   partner time to process this frame and also time to send PAUSE 
-	   frame itself.
-
-	   Here is the worst case scenario for the RX FIFO "headroom"
-	   (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
-
-	   1) One maximum-length frame on TX                    1522 bytes
-	   2