mwl8k: Marvell TOPDOG wireless driver

Add a driver for Marvell 88w8xxx TOPDOG PCI/PCIe wireless parts.
This initial version supports the 88w8687 802.11b/g PCIe part on
channels 1-11, and only STA mode is currently implemented.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

3 files changed, 3800 insertions, 0 deletions

diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 1294175cab2..612fffe100a 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -473,6 +473,15 @@ config MAC80211_HWSIM
 	  To compile this driver as a module, choose M here: the module will be
 	  called mac80211_hwsim.  If unsure, say N.
 
+config MWL8K
+	tristate "Marvell 88W8xxx PCI/PCIe Wireless support"
+	depends on MAC80211 && PCI && WLAN_80211 && EXPERIMENTAL
+	---help---
+	  This driver supports Marvell TOPDOG 802.11 wireless cards.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called mwl8k.  If unsure, say N.
+
 source "drivers/net/wireless/p54/Kconfig"
 source "drivers/net/wireless/ath5k/Kconfig"
 source "drivers/net/wireless/ath9k/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index e2574cafe05..d780487c420 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -48,6 +48,8 @@ obj-$(CONFIG_LIBERTAS_THINFIRM)	+= libertas_tf/
 
 obj-$(CONFIG_ADM8211)	+= adm8211.o
 
+obj-$(CONFIG_MWL8K)	+= mwl8k.o
+
 obj-$(CONFIG_IWLWIFI)	+= iwlwifi/
 obj-$(CONFIG_RT2X00)	+= rt2x00/
 
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
new file mode 100644
index 00000000000..57a0268d1ba
--- /dev/null
+++ b/drivers/net/wireless/mwl8k.c
@@ -0,0 +1,3789 @@
+/*
+ * drivers/net/wireless/mwl8k.c driver for Marvell TOPDOG 802.11 Wireless cards
+ *
+ * Copyright (C) 2008 Marvell Semiconductor Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/completion.h>
+#include <linux/etherdevice.h>
+#include <net/mac80211.h>
+#include <linux/moduleparam.h>
+#include <linux/firmware.h>
+#include <linux/workqueue.h>
+
+#define MWL8K_DESC	"Marvell TOPDOG(R) 802.11 Wireless Network Driver"
+#define MWL8K_NAME	KBUILD_MODNAME
+#define MWL8K_VERSION	"0.9.1"
+
+MODULE_DESCRIPTION(MWL8K_DESC);
+MODULE_VERSION(MWL8K_VERSION);
+MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
+MODULE_LICENSE("GPL");
+
+static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
+	{ PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
+	{ PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, mwl8k_table);
+
+#define IEEE80211_ADDR_LEN			ETH_ALEN
+
+/* Register definitions */
+#define MWL8K_HIU_GEN_PTR			0x00000c10
+#define  MWL8K_MODE_STA				0x0000005a
+#define  MWL8K_MODE_AP				0x000000a5
+#define MWL8K_HIU_INT_CODE			0x00000c14
+#define  MWL8K_FWSTA_READY			0xf0f1f2f4
+#define  MWL8K_FWAP_READY			0xf1f2f4a5
+#define  MWL8K_INT_CODE_CMD_FINISHED		0x00000005
+#define MWL8K_HIU_SCRATCH			0x00000c40
+
+/* Host->device communications */
+#define MWL8K_HIU_H2A_INTERRUPT_EVENTS		0x00000c18
+#define MWL8K_HIU_H2A_INTERRUPT_STATUS		0x00000c1c
+#define MWL8K_HIU_H2A_INTERRUPT_MASK		0x00000c20
+#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL	0x00000c24
+#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK	0x00000c28
+#define  MWL8K_H2A_INT_DUMMY			(1 << 20)
+#define  MWL8K_H2A_INT_RESET			(1 << 15)
+#define  MWL8K_H2A_INT_PS			(1 << 2)
+#define  MWL8K_H2A_INT_DOORBELL			(1 << 1)
+#define  MWL8K_H2A_INT_PPA_READY		(1 << 0)
+
+/* Device->host communications */
+#define MWL8K_HIU_A2H_INTERRUPT_EVENTS		0x00000c2c
+#define MWL8K_HIU_A2H_INTERRUPT_STATUS		0x00000c30
+#define MWL8K_HIU_A2H_INTERRUPT_MASK		0x00000c34
+#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL	0x00000c38
+#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK	0x00000c3c
+#define  MWL8K_A2H_INT_DUMMY			(1 << 20)
+#define  MWL8K_A2H_INT_CHNL_SWITCHED		(1 << 11)
+#define  MWL8K_A2H_INT_QUEUE_EMPTY		(1 << 10)
+#define  MWL8K_A2H_INT_RADAR_DETECT		(1 << 7)
+#define  MWL8K_A2H_INT_RADIO_ON			(1 << 6)
+#define  MWL8K_A2H_INT_RADIO_OFF		(1 << 5)
+#define  MWL8K_A2H_INT_MAC_EVENT		(1 << 3)
+#define  MWL8K_A2H_INT_OPC_DONE			(1 << 2)
+#define  MWL8K_A2H_INT_RX_READY			(1 << 1)
+#define  MWL8K_A2H_INT_TX_DONE			(1 << 0)
+
+#define MWL8K_A2H_EVENTS	(MWL8K_A2H_INT_DUMMY | \
+				 MWL8K_A2H_INT_CHNL_SWITCHED | \
+				 MWL8K_A2H_INT_QUEUE_EMPTY | \
+				 MWL8K_A2H_INT_RADAR_DETECT | \
+				 MWL8K_A2H_INT_RADIO_ON | \
+				 MWL8K_A2H_INT_RADIO_OFF | \
+				 MWL8K_A2H_INT_MAC_EVENT | \
+				 MWL8K_A2H_INT_OPC_DONE | \
+				 MWL8K_A2H_INT_RX_READY | \
+				 MWL8K_A2H_INT_TX_DONE)
+
+/* WME stream classes */
+#define WME_AC_BE	0		/* best effort */
+#define WME_AC_BK	1		/* background */
+#define WME_AC_VI	2		/* video */
+#define WME_AC_VO	3		/* voice */
+
+#define MWL8K_RX_QUEUES		1
+#define MWL8K_TX_QUEUES		4
+
+struct mwl8k_rx_queue {
+	int rx_desc_count;
+
+	/* hw receives here */
+	int rx_head;
+
+	/* refill descs here */
+	int rx_tail;
+
+	struct mwl8k_rx_desc *rx_desc_area;
+	dma_addr_t rx_desc_dma;
+	struct sk_buff **rx_skb;
+};
+
+struct mwl8k_skb {
+	/*
+	 * The DMA engine requires a modification to the payload.
+	 * If the skbuff is shared/cloned, it needs to be unshared.
+	 * This method is used to ensure the stack always gets back
+	 * the skbuff it sent for transmission.
+	 */
+	struct sk_buff *clone;
+	struct sk_buff *skb;
+};
+
+struct mwl8k_tx_queue {
+	/* hw transmits here */
+	int tx_head;
+
+	/* sw appends here */
+	int tx_tail;
+
+	struct ieee80211_tx_queue_stats tx_stats;
+	struct mwl8k_tx_desc *tx_desc_area;
+	dma_addr_t tx_desc_dma;
+	struct mwl8k_skb *tx_skb;
+};
+
+/* Pointers to the firmware data and meta information about it.  */
+struct mwl8k_firmware {
+	/* Microcode */
+	struct firmware *ucode;
+
+	/* Boot helper code */
+	struct firmware *helper;
+};
+
+struct mwl8k_priv {
+	void __iomem *regs;
+	struct ieee80211_hw *hw;
+
+	struct pci_dev *pdev;
+	u8 name[16];
+	/* firmware access lock */
+	spinlock_t fw_lock;
+
+	/* firmware files and meta data */
+	struct mwl8k_firmware fw;
+	u32 part_num;
+
+	/* lock held over TX and TX reap */
+	spinlock_t tx_lock;
+	u32 int_mask;
+
+	struct ieee80211_vif *vif;
+	struct list_head vif_list;
+
+	struct ieee80211_channel *current_channel;
+
+	/* power management status cookie from firmware */
+	u32 *cookie;
+	dma_addr_t cookie_dma;
+
+	u16 num_mcaddrs;
+	u16 region_code;
+	u8 hw_rev;
+	__le32 fw_rev;
+	u32 wep_enabled;
+
+	/*
+	 * Running count of TX packets in flight, to avoid
+	 * iterating over the transmit rings each time.
+	 */
+	int pending_tx_pkts;
+
+	struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
+	struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
+
+	/* PHY parameters */
+	struct ieee80211_supported_band band;
+	struct ieee80211_channel channels[14];
+	struct ieee80211_rate rates[12];
+
+	/* RF preamble: Short, Long or Auto */
+	u8	radio_preamble;
+	u8	radio_state;
+
+	/* WMM MODE 1 for enabled; 0 for disabled */
+	bool wmm_mode;
+
+	/* Set if PHY config is in progress */
+	bool inconfig;
+
+	/* XXX need to convert this to handle multiple interfaces */
+	bool capture_beacon;
+	u8 capture_bssid[IEEE80211_ADDR_LEN];
+	struct sk_buff *beacon_skb;
+
+	/*
+	 * This FJ worker has to be global as it is scheduled from the
+	 * RX handler.  At this point we don't know which interface it
+	 * belongs to until the list of bssids waiting to complete join
+	 * is checked.
+	 */
+	struct work_struct finalize_join_worker;
+
+	/* Tasklet to reclaim TX descriptors and buffers after tx */
+	struct tasklet_struct tx_reclaim_task;
+
+	/* Work thread to serialize configuration requests */
+	struct workqueue_struct *config_wq;
+	struct completion *hostcmd_wait;
+	struct completion *tx_wait;
+};
+
+/* Per interface specific private data */
+struct mwl8k_vif {
+	struct list_head node;
+
+	/* backpointer to parent config block */
+	struct mwl8k_priv *priv;
+
+	/* BSS config of AP or IBSS from mac80211*/
+	struct ieee80211_bss_conf bss_info;
+
+	/* BSSID of AP or IBSS */
+	u8	bssid[IEEE80211_ADDR_LEN];
+	u8	mac_addr[IEEE80211_ADDR_LEN];
+
+	/*
+	 * Subset of supported legacy rates.
+	 * Intersection of AP and STA supported rates.
+	 */
+	struct ieee80211_rate legacy_rates[12];
+
+	/* number of supported legacy rates */
+	u8	legacy_nrates;
+
+	/* Number of supported MCS rates. Work in progress */
+	u8	mcs_nrates;
+
+	 /* Index into station database.Returned by update_sta_db call */
+	u8	peer_id;
+
+	/* Non AMPDU sequence number assigned by driver */
+	u16	seqno;
+
+	/* Note:There is no channel info,
+	 * refer to the master channel info in priv
+	 */
+};
+
+#define MWL8K_VIF(_vif) (struct mwl8k_vif *)(&((_vif)->drv_priv))
+
+static const struct ieee80211_channel mwl8k_channels[] = {
+	{ .center_freq = 2412, .hw_value = 1, },
+	{ .center_freq = 2417, .hw_value = 2, },
+	{ .center_freq = 2422, .hw_value = 3, },
+	{ .center_freq = 2427, .hw_value = 4, },
+	{ .center_freq = 2432, .hw_value = 5, },
+	{ .center_freq = 2437, .hw_value = 6, },
+	{ .center_freq = 2442, .hw_value = 7, },
+	{ .center_freq = 2447, .hw_value = 8, },
+	{ .center_freq = 2452, .hw_value = 9, },
+	{ .center_freq = 2457, .hw_value = 10, },
+	{ .center_freq = 2462, .hw_value = 11, },
+};
+
+static const struct ieee80211_rate mwl8k_rates[] = {
+	{ .bitrate = 10, .hw_value = 2, },
+	{ .bitrate = 20, .hw_value = 4, },
+	{ .bitrate = 55, .hw_value = 11, },
+	{ .bitrate = 60, .hw_value = 12, },
+	{ .bitrate = 90, .hw_value = 18, },
+	{ .bitrate = 110, .hw_value = 22, },
+	{ .bitrate = 120, .hw_value = 24, },
+	{ .bitrate = 180, .hw_value = 36, },
+	{ .bitrate = 240, .hw_value = 48, },
+	{ .bitrate = 360, .hw_value = 72, },
+	{ .bitrate = 480, .hw_value = 96, },
+	{ .bitrate = 540, .hw_value = 108, },
+};
+
+/* Radio settings */
+#define MWL8K_RADIO_FORCE		0x2
+#define MWL8K_RADIO_ENABLE		0x1
+#define MWL8K_RADIO_DISABLE		0x0
+#define MWL8K_RADIO_AUTO_PREAMBLE	0x0005
+#define MWL8K_RADIO_SHORT_PREAMBLE	0x0003
+#define MWL8K_RADIO_LONG_PREAMBLE	0x0001
+
+/* WMM */
+#define MWL8K_WMM_ENABLE		1
+#define MWL8K_WMM_DISABLE		0
+
+#define MWL8K_RADIO_DEFAULT_PREAMBLE	MWL8K_RADIO_LONG_PREAMBLE
+
+/* Slot time */
+
+/* Short Slot: 9us slot time */
+#define MWL8K_SHORT_SLOTTIME		1
+
+/* Long slot: 20us slot time */
+#define MWL8K_LONG_SLOTTIME		0
+
+/* Set or get info from Firmware */
+#define MWL8K_CMD_SET			0x0001
+#define MWL8K_CMD_GET			0x0000
+
+/* Firmware command codes */
+#define MWL8K_CMD_CODE_DNLD		0x0001
+#define MWL8K_CMD_GET_HW_SPEC		0x0003
+#define MWL8K_CMD_MAC_MULTICAST_ADR	0x0010
+#define MWL8K_CMD_GET_STAT		0x0014
+#define MWL8K_CMD_RADIO_CONTROL		0x001C
+#define MWL8K_CMD_RF_TX_POWER		0x001E
+#define MWL8K_CMD_SET_PRE_SCAN		0x0107
+#define MWL8K_CMD_SET_POST_SCAN		0x0108
+#define MWL8K_CMD_SET_RF_CHANNEL	0x010A
+#define MWL8K_CMD_SET_SLOT		0x0114
+#define MWL8K_CMD_MIMO_CONFIG		0x0125
+#define MWL8K_CMD_ENABLE_SNIFFER	0x0150
+#define MWL8K_CMD_SET_WMM_MODE		0x0123
+#define MWL8K_CMD_SET_EDCA_PARAMS	0x0115
+#define MWL8K_CMD_SET_FINALIZE_JOIN	0x0111
+#define MWL8K_CMD_UPDATE_STADB		0x1123
+#define MWL8K_CMD_SET_RATEADAPT_MODE	0x0203
+#define MWL8K_CMD_SET_LINKADAPT_MODE	0x0129
+#define MWL8K_CMD_SET_AID		0x010d
+#define MWL8K_CMD_SET_RATE		0x0110
+#define MWL8K_CMD_USE_FIXED_RATE	0x0126
+#define MWL8K_CMD_RTS_THRESHOLD		0x0113
+#define MWL8K_CMD_ENCRYPTION		0x1122
+
+static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
+{
+#define MWL8K_CMDNAME(x)	case MWL8K_CMD_##x: do {\
+					snprintf(buf, bufsize, "%s", #x);\
+					return buf;\
+					} while (0)
+	switch (cmd & (~0x8000)) {
+		MWL8K_CMDNAME(CODE_DNLD);
+		MWL8K_CMDNAME(GET_HW_SPEC);
+		MWL8K_CMDNAME(MAC_MULTICAST_ADR);
+		MWL8K_CMDNAME(GET_STAT);
+		MWL8K_CMDNAME(RADIO_CONTROL);
+		MWL8K_CMDNAME(RF_TX_POWER);
+		MWL8K_CMDNAME(SET_PRE_SCAN);
+		MWL8K_CMDNAME(SET_POST_SCAN);
+		MWL8K_CMDNAME(SET_RF_CHANNEL);
+		MWL8K_CMDNAME(SET_SLOT);
+		MWL8K_CMDNAME(MIMO_CONFIG);
+		MWL8K_CMDNAME(ENABLE_SNIFFER);
+		MWL8K_CMDNAME(SET_WMM_MODE);
+		MWL8K_CMDNAME(SET_EDCA_PARAMS);
+		MWL8K_CMDNAME(SET_FINALIZE_JOIN);
+		MWL8K_CMDNAME(UPDATE_STADB);
+		MWL8K_CMDNAME(SET_RATEADAPT_MODE);
+		MWL8K_CMDNAME(SET_LINKADAPT_MODE);
+		MWL8K_CMDNAME(SET_AID);
+		MWL8K_CMDNAME(SET_RATE);
+		MWL8K_CMDNAME(USE_FIXED_RATE);
+		MWL8K_CMDNAME(RTS_THRESHOLD);
+		MWL8K_CMDNAME(ENCRYPTION);
+	default:
+		snprintf(buf, bufsize, "0x%x", cmd);
+	}
+#undef MWL8K_CMDNAME
+
+	return buf;
+}
+
+/* Hardware and firmware reset */
+static void mwl8k_hw_reset(struct mwl8k_priv *priv)
+{
+	iowrite32(MWL8K_H2A_INT_RESET,
+		priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
+	iowrite32(MWL8K_H2A_INT_RESET,
+		priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
+	msleep(20);
+}
+
+/* Release fw image */
+static void mwl8k_release_fw(struct firmware **fw)
+{
+	if (*fw == NULL)
+		return;
+	release_firmware(*fw);
+	*fw = NULL;
+}
+
+static void mwl8k_release_firmware(struct mwl8k_priv *priv)
+{
+	mwl8k_release_fw(&priv->fw.ucode);
+	mwl8k_release_fw(&priv->fw.helper);
+}
+
+/* Request fw image */
+static int mwl8k_request_fw(struct mwl8k_priv *priv,
+				const char *fname, struct firmware **fw)
+{
+	/* release current image */
+	if (*fw != NULL)
+		mwl8k_release_fw(fw);
+
+	return request_firmware((const struct firmware **)fw,
+						fname, &priv->pdev->dev);
+}
+
+static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
+{
+	u8 filename[64];
+	int rc;
+
+	priv->part_num = part_num;
+
+	snprintf(filename, sizeof(filename),
+		 "mwl8k/helper_%u.fw", priv->part_num);
+
+	rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
+	if (rc) {
+		printk(KERN_ERR
+			"%s Error requesting helper firmware file %s\n",
+			pci_name(priv->pdev), filename);
+		return rc;
+	}
+
+	snprintf(filename, sizeof(filename),
+		 "mwl8k/fmimage_%u.fw", priv->part_num);
+
+	rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
+	if (rc) {
+		printk(KERN_ERR "%s Error requesting firmware file %s\n",
+					pci_name(priv->pdev), filename);
+		mwl8k_release_fw(&priv->fw.helper);
+		return rc;
+	}
+
+	return 0;
+}
+
+struct mwl8k_cmd_pkt {
+	__le16	code;
+	__le16	length;
+	__le16	seq_num;
+	__le16	result;
+	char	payload[0];
+} __attribute__((packed));
+
+/*
+ * Firmware loading.
+ */
+static int
+mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
+{
+	void __iomem *regs = priv->regs;
+	dma_addr_t dma_addr;
+	int rc;
+	int loops;
+
+	dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
+	if (pci_dma_mapping_error(priv->pdev, dma_addr))
+		return -ENOMEM;
+
+	iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
+	iowrite32(0, regs + MWL8K_HIU_INT_CODE);
+	iowrite32(MWL8K_H2A_INT_DOORBELL,
+		regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
+	iowrite32(MWL8K_H2A_INT_DUMMY,
+		regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
+
+	rc = -ETIMEDOUT;
+	loops = 1000;
+	do {
+		u32 int_code;
+
+		int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
+		if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
+			iowrite32(0, regs + MWL8K_HIU_INT_CODE);
+			rc = 0;
+			break;
+		}
+
+		udelay(1);
+	} while (--loops);
+
+	pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
+
+	/*
+	 * Clear 'command done' interrupt bit.
+	 */
+	loops = 1000;
+	do {
+		u32 status;
+
+		status = ioread32(priv->regs +
+				MWL8K_HIU_A2H_INTERRUPT_STATUS);
+		if (status & MWL8K_A2H_INT_OPC_DONE) {
+			iowrite32(~MWL8K_A2H_INT_OPC_DONE,
+				priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
+			ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
+			break;
+		}
+
+		udelay(1);
+	} while (--loops);
+
+	return rc;
+}
+
+static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
+				const u8 *data, size_t length)
+{
+	struct mwl8k_cmd_pkt *cmd;
+	int done;
+	int rc = 0;
+
+	cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
+	if (cmd == NULL)
+		return -ENOMEM;
+
+	cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
+	cmd->seq_num = 0;
+	cmd->result = 0;
+
+	done = 0;
+	while (length) {
+		int block_size = length > 256 ? 256 : length;
+
+		memcpy(cmd->payload, data + done, block_size);
+		cmd->length = cpu_to_le16(block_size);
+
+		rc = mwl8k_send_fw_load_cmd(priv, cmd,
+						sizeof(*cmd) + block_size);
+		if (rc)
+			break;
+
+		done += block_size;
+		length -= block_size;
+	}
+
+	if (!rc) {
+		cmd->length = 0;
+		rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
+	}
+
+	kfree(cmd);
+
+	return rc;
+}
+
+static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
+				const u8 *data, size_t length)
+{
+	unsigned char *buffer;
+	int may_continue, rc = 0;
+	u32 done, prev_block_size;
+
+	buffer = kmalloc(1024, GFP_KERNEL);
+	if (buffer == NULL)
+		return -ENOMEM;
+
+	done = 0;
+	prev_block_size = 0;
+	may_continue = 1000;
+	while (may_continue > 0) {
+		u32 block_size;
+
+		block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
+		if (block_size & 1) {
+			block_size &= ~1;
+			may_continue--;
+		} else {
+			done += prev_block_size;
+			length -= prev_block_size;
+		}
+
+		if (block_size > 1024 || block_size > length) {
+			rc = -EOVERFLOW;
+			break;
+		}
+
+		if (length == 0) {
+			rc = 0;
+			break;
+		}
+
+		if (block_size == 0) {
+			rc = -EPROTO;
+			may_continue--;
+			udelay(1);
+			continue;
+		}
+
+		prev_block_size = block_size;
+		memcpy(buffer, data + done, block_size);
+
+		rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
+		if (rc)
+			break;
+	}
+
+	if (!rc && length != 0)
+		rc = -EREMOTEIO;
+
+	kfree(buffer);
+
+	return rc;
+}
+
+static int mwl8k_load_firmware(struct mwl8k_priv *priv)
+{
+	int loops, rc;
+
+	const u8 *ucode = priv->fw.ucode->data;
+	size_t ucode_len = priv->fw.ucode->size;
+	const u8 *helper = priv->fw.helper->data;
+	size_t helper_len = priv->fw.helper->size;
+
+	if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
+		rc = mwl8k_load_fw_image(priv, helper, helper_len);
+		if (rc) {
+			printk(KERN_ERR "%s: unable to load firmware "
+				"helper image\n", pci_name(priv->pdev));
+			return rc;
+		}
+		msleep(1);
+
+		rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
+	} else {
+		rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
+	}
+
+	if (rc) {
+		printk(KERN_ERR "%s: unable to load firmware data\n",
+			pci_name(priv->pdev));
+		return rc;
+	}
+
+	iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
+	msleep(1);
+
+	loops = 200000;
+	do {
+		if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
+						== MWL8K_FWSTA_READY)
+			break;
+		udelay(1);
+	} while (--loops);
+
+	return loops ? 0 : -ETIMEDOUT;
+}
+
+
+/*
+ * Defines shared between transmission and reception.
+ */
+/* HT control fields for firmware */
+struct ewc_ht_info {
+	__le16	control1;
+	__le16	control2;
+	__le16	control3;
+} __attribute__((packed));
+
+/* Firmware Station database operations */
+#define MWL8K_STA_DB_ADD_ENTRY		0
+#define MWL8K_STA_DB_MODIFY_ENTRY	1
+#define MWL8K_STA_DB_DEL_ENTRY		2
+#define MWL8K_STA_DB_FLUSH		3
+
+/* Peer Entry flags - used to define the type of the peer node */
+#define MWL8K_PEER_TYPE_ACCESSPOINT	2
+#define MWL8K_PEER_TYPE_ADHOC_STATION	4
+
+#define MWL8K_IEEE_LEGACY_DATA_RATES	12
+#define MWL8K_MCS_BITMAP_SIZE		16
+#define pad_size			16
+
+struct peer_capability_info {
+	/* Peer type - AP vs. STA.  */
+	__u8	peer_type;
+
+	/* Basic 802.11 capabilities from assoc resp.  */
+	__le16	basic_caps;
+
+	/* Set if peer supports 802.11n high throughput (HT).  */
+	__u8	ht_support;
+
+	/* Valid if HT is supported.  */
+	__le16	ht_caps;
+	__u8	extended_ht_caps;
+	struct ewc_ht_info	ewc_info;
+
+	/* Legacy rate table. Intersection of our rates and peer rates.  */
+	__u8	legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
+
+	/* HT rate table. Intersection of our rates and peer rates.  */
+	__u8	ht_rates[MWL8K_MCS_BITMAP_SIZE];
+	__u8	pad[pad_size];
+
+	/* If set, interoperability mode, no proprietary extensions.  */
+	__u8	interop;
+	__u8	pad2;
+	__u8	station_id;
+	__le16	amsdu_enabled;
+} __attribute__((packed));
+
+/* Inline functions to manipulate QoS field in data descriptor.  */
+static inline u16 mwl8k_qos_setbit_tid(u16 qos, u8 tid)
+{
+	u16 val_mask = 0x000f;
+	u16 qos_mask = ~val_mask;
+
+	/* TID bits 0-3 */
+	return (qos & qos_mask) | (tid & val_mask);
+}
+
+static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
+{
+	u16 val_mask = 1 << 4;
+
+	/* End of Service Period Bit 4 */
+	return qos | val_mask;
+}
+
+static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
+{
+	u16 val_mask = 0x3;
+	u8	shift = 5;
+	u16 qos_mask = ~(val_mask << shift);
+
+	/* Ack Policy Bit 5-6 */
+	return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
+}
+
+static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
+{
+	u16 val_mask = 1 << 7;
+
+	/* AMSDU present Bit 7 */
+	return qos | val_mask;
+}
+
+static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
+{
+	u16 val_mask = 0xff;
+	u8	shift = 8;
+	u16 qos_mask = ~(val_mask << shift);
+
+	/* Queue Length Bits 8-15 */
+	return (qos & qos_mask) | ((len & val_mask) << shift);
+}
+
+/* DMA header used by firmware and hardware.  */
+struct mwl8k_dma_data {
+	__le16 fwlen;
+	struct ieee80211_hdr wh;
+} __attribute__((packed));
+
+/* Routines to add/remove DMA header from skb.  */
+static inline int mwl8k_remove_dma_header(struct sk_buff *skb)
+{
+	struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)(skb->data);
+	void *dst, *src = &tr->wh;
+	__le16 fc = tr->wh.frame_control;
+	int hdrlen = ieee80211_hdrlen(fc);
+	u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
+
+	dst = (void *)tr + space;
+	if (dst != src) {
+		memmove(dst, src, hdrlen);
+		skb_pull(skb, space);
+	}
+
+	return 0;
+}
+
+static inline struct sk_buff *mwl8k_add_dma_header(struct sk_buff *skb)
+{
+	struct ieee80211_hdr *wh;
+	u32 hdrlen, pktlen;
+	struct mwl8k_dma_data *tr;
+
+	wh = (struct ieee80211_hdr *)skb->data;
+	hdrlen = ieee80211_hdrlen(wh->frame_control);
+	pktlen = skb->len;
+
+	/*
+	 * Copy up/down the 802.11 header; the firmware requires
+	 * we present a 2-byte payload length followed by a
+	 * 4-address header (w/o QoS), followed (optionally) by
+	 * any WEP/ExtIV header (but only filled in for CCMP).
+	 */
+	if (hdrlen != sizeof(struct mwl8k_dma_data))
+		skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
+
+	tr = (struct mwl8k_dma_data *)skb->data;
+	if (wh != &tr->wh)
+		memmove(&tr->wh, wh, hdrlen);
+
+	/* Clear addr4 */
+	memset(tr->wh.addr4, 0, IEEE80211_ADDR_LEN);
+
+	/*
+	 * Firmware length is the length of the fully formed "802.11
+	 * payload".  That is, everything except for the 802.11 header.
+	 * This includes all crypto material including the MIC.
+	 */
+	tr->fwlen = cpu_to_le16(pktlen - hdrlen);
+
+	return skb;
+}
+
+
+/*
+ * Packet reception.
+ */
+#define MWL8K_RX_CTRL_KEY_INDEX_MASK	0x30
+#define MWL8K_RX_CTRL_OWNED_BY_HOST	0x02
+#define MWL8K_RX_CTRL_AMPDU		0x01
+
+struct mwl8k_rx_desc {
+	__le16 pkt_len;
+	__u8 link_quality;
+	__u8 noise_level;
+	__le32 pkt_phys_addr;
+	__le32 next_rx_desc_phys_addr;
+	__le16 qos_control;
+	__le16 rate_info;
+	__le32 pad0[4];
+	__u8 rssi;
+	__u8 channel;
+	__le16 pad1;
+	__u8 rx_ctrl;
+	__u8 rx_status;
+	__u8 pad2[2];
+} __attribute__((packed));
+
+#define MWL8K_RX_DESCS		256
+#define MWL8K_RX_MAXSZ		3800
+
+static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
+{
+	struct mwl8k_priv *priv = hw->priv;
+	struct mwl8k_rx_queue *rxq = priv->rxq + index;
+	int size;
+	int i;
+
+	rxq->rx_desc_count = 0;
+	rxq->rx_head = 0;
+	rxq->rx_tail = 0;
+
+	size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
+
+	rxq->rx_desc_area =
+		pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
+	if (rxq->rx_desc_area == NULL) {
+		printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
+		       priv->name);
+		return -ENOMEM;
+	}
+	memset(rxq->rx_desc_area, 0, size);
+
+	rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
+				sizeof(*rxq->rx_skb), GFP_KERNEL);
+	if (rxq->rx_skb == NULL) {
+		printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
+			priv->name);
+		pci_free_consistent(priv->pdev, size,
+				    rxq->rx_desc_area, rxq->rx_desc_dma);
+		return -ENOMEM;
+	}
+	memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
+
+	for (i = 0; i < MWL8K_RX_DESCS; i++) {
+		struct mwl8k_rx_desc *rx_desc;
+		int nexti;
+
+		rx_desc = rxq->rx_desc_area + i;
+		nexti = (i + 1) % MWL8K_RX_DESCS;
+
+		rx_desc->next_rx_desc_phys_addr =
+			cpu_to_le32(rxq->rx_desc_dma
+						+ nexti * sizeof(*rx_desc));
+		rx_desc->rx_ctrl =
+			cpu_to_le32(MWL8K_RX_CTRL_OWNED_BY_HOST);
+	}
+
+	return 0;
+}
+
+static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
+{
+	struct mwl8k_priv *priv = hw->priv;
+	struct mwl8k_rx_queue *rxq = priv->rxq + index;
+	int refilled;
+
+	refilled = 0;
+	while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
+		struct sk_buff *skb;
+		int rx;
+
+		skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
+		if (skb == NULL)
+			break;
+
+		rxq->rx_desc_count++;
+
+		rx = rxq->rx_tail;
+		rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
+
+		rxq->rx_desc_area[rx].pkt_phys_addr =
+			cpu_to_le32(pci_map_single(priv->pdev, skb->data,
+					MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
+
+		rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
+		rxq->rx_skb[rx] = skb;
+		wmb();
+		rxq->rx_desc_area[rx].rx_ctrl = 0;
+
+		refilled++;
+	}
+
+	return refilled;
+}
+
+/* Must be called only when the card's reception is completely halted */
+static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
+{
+	struct mwl8k_priv *priv = hw->priv;
+	struct mwl8k_rx_queue *rxq = priv->rxq + index;
+	int i;
+
+	for (i = 0; i < MWL8K_RX_DESCS; i++) {
+		if (rxq->rx_skb[i] != NULL) {
+			unsigned long addr;
+
+			addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
+			pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
+					 PCI_DMA_FROMDEVICE);
+			kfree_skb(rxq->rx_skb[i]);
+			rxq->rx_skb[i] = NULL;
+		}
+	}
+
+	kfree(rxq->rx_skb);
+	rxq->rx_skb = NULL;
+
+	pci_free_consistent(priv->pdev,
+			    MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
+			    rxq->rx_desc_area, rxq->rx_desc_dma);
+	rxq->rx_desc_area = NULL;
+}
+
+
+/*
+ * Scan a list of BSSIDs to process for finalize join.
+ * Allows for extension to process multiple BSSIDs.
+ */
+static inline int
+mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
+{
+	return priv->capture_beacon &&
+		ieee80211_is_beacon(wh->frame_control) &&
+		!compare_ether_addr(wh->addr3, priv->capture_bssid);
+}
+
+static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
+							struct sk_buff *skb)
+{
+	priv->capture_beacon = false;
+	memset(priv->capture_bssid, 0, IEEE80211_ADDR_LEN);
+
+	/*
+	 * Use GFP_ATOMIC as rxq_process is called from
+	 * the primary interrupt handler, memory allocation call
+	 * must not sleep.
+	 */
+	priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
+	if (priv->beacon_skb != NULL)
+		queue_work(priv->config_wq,
+				&priv->finalize_join_worker);
+}
+
+static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
+{
+	struct mwl8k_priv *priv = hw->priv;
+	struct mwl8k_rx_queue *rxq = priv->rxq + index;
+	int processed;
+
+	processed = 0;
+	while (rxq->rx_desc_count && limit--) {
+		struct mwl8k_rx_desc *rx_desc;
+		struct sk_buff *skb;
+		struct ieee80211_rx_status status;
+		unsigned long addr;
+		struct ieee80211_hdr *wh;
+
+		rx_desc = rxq->rx_desc_area + rxq->rx_head;
+		if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
+			break;
+		rmb();
+
+		skb = rxq->rx_skb[rxq->rx_head];
+		rxq->rx_skb[rxq->rx_head] = NULL;
+
+		rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
+		rxq->rx_desc_count--;
+
+		addr = le32_to_cpu(rx_desc->pkt_phys_addr);
+		pci_unmap_single(priv->pdev, addr,
+					MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
+
+		skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
+		if (mwl8k_remove_dma_header(skb)) {
+			dev_kfree_skb(skb);
+			continue;
+		}
+
+		wh = (struct ieee80211_hdr *)skb->data;
+
+		/*
+		 * Check for pending join operation. save a copy of
+		 * the beacon and schedule a tasklet to send finalize
+		 * join command to the firmware.
+		 */
+		if (mwl8k_capture_bssid(priv, wh))
+			mwl8k_save_beacon(priv, skb);
+
+		memset(&status, 0, sizeof(status));
+		status.mactime = 0;
+		status.signal = -rx_desc->rssi;
+		status.noise = -rx_desc->noise_level;
+		status.qual = rx_desc->link_quality;
+		status.antenna = 1;
+		status.rate_idx = 1;
+		status.flag = 0;
+		status.band = IEEE80211_BAND_2GHZ;
+		status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
+		ieee80211_rx_irqsafe(hw, skb, &status);
+
+		processed++;
+	}
+
+	return processed;
+}
+
+
+/*
+ * Packet transmission.
+ */
+
+/* Transmit queue assignment.  */
+enum {
+	MWL8K_WME_AC_BK	= 0,		/* background access */
+	MWL8K_WME_AC_BE	= 1,		/* best effort access */
+	MWL8K_WME_AC_VI	= 2,		/* video access */
+	MWL8K_WME_AC_VO	= 3,		/* voice access */
+};
+
+/* Transmit packet ACK policy */
+#define MWL8K_TXD_ACK_POLICY_NORMAL		0
+#define MWL8K_TXD_ACK_POLICY_NONE		1
+#define MWL8K_TXD_ACK_POLICY_NO_EXPLICIT	2
+#define MWL8K_TXD_ACK_POLICY_BLOCKACK		3
+
+#define GET_TXQ(_ac) (\
+		((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
+		((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
+		((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
+		MWL8K_WME_AC_BE)
+
+#define MWL8K_TXD_STATUS_IDLE			0x00000000
+#define MWL8K_TXD_STATUS_USED			0x00000001
+#define MWL8K_TXD_STATUS_OK			0x00000001
+#define MWL8K_TXD_STATUS_OK_RETRY		0x00000002
+#define MWL8K_TXD_STATUS_OK_MORE_RETRY		0x00000004
+#define MWL8K_TXD_STATUS_MULTICAST_TX		0x00000008
+#define MWL8K_TXD_STATUS_BROADCAST_TX		0x00000010
+#define MWL8K_TXD_STATUS_FAILED_LINK_ERROR	0x00000020
+#define MWL8K_TXD_STATUS_FAILED_EXCEED_LIMIT	0x00000040
+#define MWL8K_TXD_STATUS_FAILED_AGING		0x00000080
+#define MWL8K_TXD_STATUS_HOST_CMD		0x40000000
+#define MWL8K_TXD_STATUS_FW_OWNED		0x80000000
+#define  MWL8K_TXD_SOFTSTALE				0x80
+#define  MWL8K_TXD_SOFTSTALE_MGMT_RETRY			0x01
+
+struct mwl8k_tx_desc {
+	__le32 status;
+	__u8 data_rate;
+	__u8 tx_priority;
+	__le16 qos_control;
+	__le32 pkt_phys_addr;
+	__le16 pkt_len;
+	__u8 dest_MAC_addr[IEEE80211_ADDR_LEN];
+	__le32 next_tx_desc_phys_addr;
+	__le32 reserved;
+	__le16 rate_info;
+	__u8 peer_id;
+	__u8 tx_frag_cnt;
+} __attribute__((packed));
+
+#define MWL8K_TX_DESCS		128
+
+static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
+{
+	struct mwl8k_priv *priv = hw->priv;
+	struct mwl8k_tx_queue *txq = priv->txq + index;
+	int size;
+	int i;
+
+	memset(&txq->tx_stats, 0,
+		sizeof(struct ieee80211_tx_queue_stats));
+	txq->tx_stats.limit = MWL8K_TX_DESCS;
+	txq->tx_head = 0;
+	txq->tx_tail = 0;
+
+	size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
+
+	txq->tx_desc_area =
+		pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
+	if (txq->tx_desc_area == NULL) {
+		printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
+		       priv->name);
+		return -ENOMEM;
+	}
+	memset(txq->tx_desc_area, 0, size);
+
+	txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx