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authorSenthil Balasubramanian <senthilkumar@atheros.com>2010-11-11 00:40:33 -0800
committerJohn W. Linville <linville@tuxdriver.com>2010-11-16 16:37:05 -0500
commita9d85fbd3e5f7a0679e6276953cd23ac7bb72789 (patch)
tree4e7ba4d50219a8a493ff509b596f28a2581db0df /drivers/net/wireless/ath/ath9k/reg.h
parent72a801103f07182c0a4f3a761caa62b4ab8eb4e5 (diff)
ath9k_hw: Fix a reset failure on AR9382 (2x2).
AR9382 needs to be configured for the correct chain mask before running AGC/TxIQ caliberation. Otherwise reset would fail. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 42976b0a01c..ac6a13e2735 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1065,6 +1065,8 @@ enum {
#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
#define AR_INTR_PRIO_SYNC_MASK 0x40cc
#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_ENT_OTP 0x40d8
+#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
#define AR_RTC_9300_PLL_DIV 0x000003ff
#define AR_RTC_9300_PLL_DIV_S 0