diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-07-11 09:31:45 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-07-11 17:07:43 -0700 |
| commit | 702e52ccd32164a09ea91aa5896ad7c64cb708cb (patch) | |
| tree | 72b59ed42c59b046423a371c4d9eed330766410f /drivers/net/tg3.h | |
| parent | 6867c843813a801d5f568b6fb006695316714f1b (diff) | |
tg3: Revert PCIe tx glitch fix
This patch reverts commit 52cdf8526fe24f11d300b75458ddee017f3f4c88,
entitled "tg3: Prevent a PCIe tx glitch". The problem does not have
any visible side-effects and happens too early for the driver to do
anything about it. The proper place for this code is within the
device's bootcode.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index be7ab91f4dd..0432399ca74 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -2032,31 +2032,9 @@ /* Currently this is fixed. */ -#define TG3_PHY_PCIE_ADDR 0x00 #define TG3_PHY_MII_ADDR 0x01 -/*** Tigon3 specific PHY PCIE registers. ***/ - -#define TG3_PCIEPHY_BLOCK_ADDR 0x1f -#define TG3_PCIEPHY_XGXS_BLK1 0x0801 -#define TG3_PCIEPHY_TXB_BLK 0x0861 -#define TG3_PCIEPHY_BLOCK_SHIFT 4 - -/* TG3_PCIEPHY_TXB_BLK */ -#define TG3_PCIEPHY_TX0CTRL1 0x15 -#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003 -#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008 -#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030 -#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040 -#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400 - -/* TG3_PCIEPHY_XGXS_BLK1 */ -#define TG3_PCIEPHY_PWRMGMT4 0x1a -#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038 -#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000 - - /*** Tigon3 specific PHY MII registers. ***/ #define TG3_BMCR_SPEED1000 0x0040 |