diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2011-07-20 10:20:51 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-07-21 12:36:15 -0700 |
| commit | be671947b5b3efc6863ff429c1f265aa38e291db (patch) | |
| tree | a4e7185bbef150246ab416ebd55d8dcb0ff759d8 /drivers/net/tg3.c | |
| parent | 9e975cc291d80d5e4562d6bed15ec171e896d69b (diff) | |
tg3: Fix link flap at 100Mbps with EEE enabled
This patch increases the scope of the EEE interoperability workaround
to include more asic revisions. The workarond value is tuned to
workaround a link flap issue at 100Mbps.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 5bf7671dc2b..2a9ab99baaf 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -3131,15 +3131,16 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { case ASIC_REV_5717: case ASIC_REV_57765: - if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) - tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | - MII_TG3_DSP_CH34TP2_HIBW01); - /* Fall through */ case ASIC_REV_5719: val = MII_TG3_DSP_TAP26_ALNOKO | MII_TG3_DSP_TAP26_RMRXSTO | MII_TG3_DSP_TAP26_OPCSINPT; tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); + /* Fall through */ + case ASIC_REV_5720: + if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) + tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | + MII_TG3_DSP_CH34TP2_HIBW01); } val = 0; |