Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.26

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.26: (1090 commits)
  [NET]: Fix and allocate less memory for ->priv'less netdevices
  [IPV6]: Fix dangling references on error in fib6_add().
  [NETLABEL]: Fix NULL deref in netlbl_unlabel_staticlist_gen() if ifindex not found
  [PKT_SCHED]: Fix datalen check in tcf_simp_init().
  [INET]: Uninline the __inet_inherit_port call.
  [INET]: Drop the inet_inherit_port() call.
  SCTP: Initialize partial_bytes_acked to 0, when all of the data is acked.
  [netdrvr] forcedeth: internal simplifications; changelog removal
  phylib: factor out get_phy_id from within get_phy_device
  PHY: add BCM5464 support to broadcom PHY driver
  cxgb3: Fix __must_check warning with dev_dbg.
  tc35815: Statistics cleanup
  natsemi: fix MMIO for PPC 44x platforms
  [TIPC]: Cleanup of TIPC reference table code
  [TIPC]: Optimized initialization of TIPC reference table
  [TIPC]: Remove inlining of reference table locking routines
  e1000: convert uint16_t style integers to u16
  ixgb: convert uint16_t style integers to u16
  sb1000.c: make const arrays static
  sb1000.c: stop inlining largish static functions
  ...

1 files changed, 601 insertions, 1100 deletions

diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index 370d329d15d..10e4e85da3f 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -23,9 +23,9 @@
  */
 
 #ifdef TC35815_NAPI
-#define DRV_VERSION	"1.36-NAPI"
+#define DRV_VERSION	"1.37-NAPI"
 #else
-#define DRV_VERSION	"1.36"
+#define DRV_VERSION	"1.37"
 #endif
 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
 #define MODNAME			"tc35815"
@@ -47,8 +47,8 @@ static const char *version = "tc35815.c:v" DRV_VERSION "\n";
 #include <linux/skbuff.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
-#include <linux/mii.h>
-#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/workqueue.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
 #include <asm/byteorder.h>
@@ -60,16 +60,16 @@ static const char *version = "tc35815.c:v" DRV_VERSION "\n";
 #define WORKAROUND_100HALF_PROMISC
 /* #define TC35815_USE_PACKEDBUFFER */
 
-typedef enum {
+enum tc35815_chiptype {
 	TC35815CF = 0,
 	TC35815_NWU,
 	TC35815_TX4939,
-} board_t;
+};
 
-/* indexed by board_t, above */
+/* indexed by tc35815_chiptype, above */
 static const struct {
 	const char *name;
-} board_info[] __devinitdata = {
+} chip_info[] __devinitdata = {
 	{ "TOSHIBA TC35815CF 10/100BaseTX" },
 	{ "TOSHIBA TC35815 with Wake on LAN" },
 	{ "TOSHIBA TC35815/TX4939" },
@@ -81,209 +81,208 @@ static const struct pci_device_id tc35815_pci_tbl[] = {
 	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
 	{0,}
 };
-MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
+MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
 
 /* see MODULE_PARM_DESC */
 static struct tc35815_options {
 	int speed;
 	int duplex;
-	int doforce;
 } options;
 
 /*
  * Registers
  */
 struct tc35815_regs {
-	volatile __u32 DMA_Ctl;		/* 0x00 */
-	volatile __u32 TxFrmPtr;
-	volatile __u32 TxThrsh;
-	volatile __u32 TxPollCtr;
-	volatile __u32 BLFrmPtr;
-	volatile __u32 RxFragSize;
-	volatile __u32 Int_En;
-	volatile __u32 FDA_Bas;
-	volatile __u32 FDA_Lim;		/* 0x20 */
-	volatile __u32 Int_Src;
-	volatile __u32 unused0[2];
-	volatile __u32 PauseCnt;
-	volatile __u32 RemPauCnt;
-	volatile __u32 TxCtlFrmStat;
-	volatile __u32 unused1;
-	volatile __u32 MAC_Ctl;		/* 0x40 */
-	volatile __u32 CAM_Ctl;
-	volatile __u32 Tx_Ctl;
-	volatile __u32 Tx_Stat;
-	volatile __u32 Rx_Ctl;
-	volatile __u32 Rx_Stat;
-	volatile __u32 MD_Data;
-	volatile __u32 MD_CA;
-	volatile __u32 CAM_Adr;		/* 0x60 */
-	volatile __u32 CAM_Data;
-	volatile __u32 CAM_Ena;
-	volatile __u32 PROM_Ctl;
-	volatile __u32 PROM_Data;
-	volatile __u32 Algn_Cnt;
-	volatile __u32 CRC_Cnt;
-	volatile __u32 Miss_Cnt;
+	__u32 DMA_Ctl;		/* 0x00 */
+	__u32 TxFrmPtr;
+	__u32 TxThrsh;
+	__u32 TxPollCtr;
+	__u32 BLFrmPtr;
+	__u32 RxFragSize;
+	__u32 Int_En;
+	__u32 FDA_Bas;
+	__u32 FDA_Lim;		/* 0x20 */
+	__u32 Int_Src;
+	__u32 unused0[2];
+	__u32 PauseCnt;
+	__u32 RemPauCnt;
+	__u32 TxCtlFrmStat;
+	__u32 unused1;
+	__u32 MAC_Ctl;		/* 0x40 */
+	__u32 CAM_Ctl;
+	__u32 Tx_Ctl;
+	__u32 Tx_Stat;
+	__u32 Rx_Ctl;
+	__u32 Rx_Stat;
+	__u32 MD_Data;
+	__u32 MD_CA;
+	__u32 CAM_Adr;		/* 0x60 */
+	__u32 CAM_Data;
+	__u32 CAM_Ena;
+	__u32 PROM_Ctl;
+	__u32 PROM_Data;
+	__u32 Algn_Cnt;
+	__u32 CRC_Cnt;
+	__u32 Miss_Cnt;
 };
 
 /*
  * Bit assignments
  */
 /* DMA_Ctl bit asign ------------------------------------------------------- */
-#define DMA_RxAlign            0x00c00000 /* 1:Reception Alignment           */
-#define DMA_RxAlign_1          0x00400000
-#define DMA_RxAlign_2          0x00800000
-#define DMA_RxAlign_3          0x00c00000
-#define DMA_M66EnStat          0x00080000 /* 1:66MHz Enable State            */
-#define DMA_IntMask            0x00040000 /* 1:Interupt mask                 */
-#define DMA_SWIntReq           0x00020000 /* 1:Software Interrupt request    */
-#define DMA_TxWakeUp           0x00010000 /* 1:Transmit Wake Up              */
-#define DMA_RxBigE             0x00008000 /* 1:Receive Big Endian            */
-#define DMA_TxBigE             0x00004000 /* 1:Transmit Big Endian           */
-#define DMA_TestMode           0x00002000 /* 1:Test Mode                     */
-#define DMA_PowrMgmnt          0x00001000 /* 1:Power Management              */
-#define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size                  */
+#define DMA_RxAlign	       0x00c00000 /* 1:Reception Alignment	     */
+#define DMA_RxAlign_1	       0x00400000
+#define DMA_RxAlign_2	       0x00800000
+#define DMA_RxAlign_3	       0x00c00000
+#define DMA_M66EnStat	       0x00080000 /* 1:66MHz Enable State	     */
+#define DMA_IntMask	       0x00040000 /* 1:Interupt mask		     */
+#define DMA_SWIntReq	       0x00020000 /* 1:Software Interrupt request    */
+#define DMA_TxWakeUp	       0x00010000 /* 1:Transmit Wake Up		     */
+#define DMA_RxBigE	       0x00008000 /* 1:Receive Big Endian	     */
+#define DMA_TxBigE	       0x00004000 /* 1:Transmit Big Endian	     */
+#define DMA_TestMode	       0x00002000 /* 1:Test Mode		     */
+#define DMA_PowrMgmnt	       0x00001000 /* 1:Power Management		     */
+#define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size		     */
 
 /* RxFragSize bit asign ---------------------------------------------------- */
-#define RxFrag_EnPack          0x00008000 /* 1:Enable Packing                */
-#define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment                */
+#define RxFrag_EnPack	       0x00008000 /* 1:Enable Packing		     */
+#define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment		     */
 
 /* MAC_Ctl bit asign ------------------------------------------------------- */
-#define MAC_Link10             0x00008000 /* 1:Link Status 10Mbits           */
-#define MAC_EnMissRoll         0x00002000 /* 1:Enable Missed Roll            */
-#define MAC_MissRoll           0x00000400 /* 1:Missed Roll                   */
-#define MAC_Loop10             0x00000080 /* 1:Loop 10 Mbps                  */
-#define MAC_Conn_Auto          0x00000000 /*00:Connection mode (Automatic)   */
-#define MAC_Conn_10M           0x00000020 /*01:                (10Mbps endec)*/
-#define MAC_Conn_Mll           0x00000040 /*10:                (Mll clock)   */
-#define MAC_MacLoop            0x00000010 /* 1:MAC Loopback                  */
-#define MAC_FullDup            0x00000008 /* 1:Full Duplex 0:Half Duplex     */
-#define MAC_Reset              0x00000004 /* 1:Software Reset                */
-#define MAC_HaltImm            0x00000002 /* 1:Halt Immediate                */
-#define MAC_HaltReq            0x00000001 /* 1:Halt request                  */
+#define MAC_Link10	       0x00008000 /* 1:Link Status 10Mbits	     */
+#define MAC_EnMissRoll	       0x00002000 /* 1:Enable Missed Roll	     */
+#define MAC_MissRoll	       0x00000400 /* 1:Missed Roll		     */
+#define MAC_Loop10	       0x00000080 /* 1:Loop 10 Mbps		     */
+#define MAC_Conn_Auto	       0x00000000 /*00:Connection mode (Automatic)   */
+#define MAC_Conn_10M	       0x00000020 /*01:		       (10Mbps endec)*/
+#define MAC_Conn_Mll	       0x00000040 /*10:		       (Mll clock)   */
+#define MAC_MacLoop	       0x00000010 /* 1:MAC Loopback		     */
+#define MAC_FullDup	       0x00000008 /* 1:Full Duplex 0:Half Duplex     */
+#define MAC_Reset	       0x00000004 /* 1:Software Reset		     */
+#define MAC_HaltImm	       0x00000002 /* 1:Halt Immediate		     */
+#define MAC_HaltReq	       0x00000001 /* 1:Halt request		     */
 
 /* PROM_Ctl bit asign ------------------------------------------------------ */
-#define PROM_Busy              0x00008000 /* 1:Busy (Start Operation)        */
-#define PROM_Read              0x00004000 /*10:Read operation                */
-#define PROM_Write             0x00002000 /*01:Write operation               */
-#define PROM_Erase             0x00006000 /*11:Erase operation               */
-                                          /*00:Enable or Disable Writting,   */
-                                          /*      as specified in PROM_Addr. */
-#define PROM_Addr_Ena          0x00000030 /*11xxxx:PROM Write enable         */
-                                          /*00xxxx:           disable        */
+#define PROM_Busy	       0x00008000 /* 1:Busy (Start Operation)	     */
+#define PROM_Read	       0x00004000 /*10:Read operation		     */
+#define PROM_Write	       0x00002000 /*01:Write operation		     */
+#define PROM_Erase	       0x00006000 /*11:Erase operation		     */
+					  /*00:Enable or Disable Writting,   */
+					  /*	  as specified in PROM_Addr. */
+#define PROM_Addr_Ena	       0x00000030 /*11xxxx:PROM Write enable	     */
+					  /*00xxxx:	      disable	     */
 
 /* CAM_Ctl bit asign ------------------------------------------------------- */
-#define CAM_CompEn             0x00000010 /* 1:CAM Compare Enable            */
-#define CAM_NegCAM             0x00000008 /* 1:Reject packets CAM recognizes,*/
-                                          /*                    accept other */
-#define CAM_BroadAcc           0x00000004 /* 1:Broadcast assept              */
-#define CAM_GroupAcc           0x00000002 /* 1:Multicast assept              */
-#define CAM_StationAcc         0x00000001 /* 1:unicast accept                */
+#define CAM_CompEn	       0x00000010 /* 1:CAM Compare Enable	     */
+#define CAM_NegCAM	       0x00000008 /* 1:Reject packets CAM recognizes,*/
+					  /*			accept other */
+#define CAM_BroadAcc	       0x00000004 /* 1:Broadcast assept		     */
+#define CAM_GroupAcc	       0x00000002 /* 1:Multicast assept		     */
+#define CAM_StationAcc	       0x00000001 /* 1:unicast accept		     */
 
 /* CAM_Ena bit asign ------------------------------------------------------- */
-#define CAM_ENTRY_MAX                  21   /* CAM Data entry max count      */
+#define CAM_ENTRY_MAX		       21   /* CAM Data entry max count	     */
 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
-#define CAM_Ena_Bit(index)         (1<<(index))
+#define CAM_Ena_Bit(index)	(1 << (index))
 #define CAM_ENTRY_DESTINATION	0
 #define CAM_ENTRY_SOURCE	1
 #define CAM_ENTRY_MACCTL	20
 
 /* Tx_Ctl bit asign -------------------------------------------------------- */
-#define Tx_En                  0x00000001 /* 1:Transmit enable               */
-#define Tx_TxHalt              0x00000002 /* 1:Transmit Halt Request         */
-#define Tx_NoPad               0x00000004 /* 1:Suppress Padding              */
-#define Tx_NoCRC               0x00000008 /* 1:Suppress Padding              */
-#define Tx_FBack               0x00000010 /* 1:Fast Back-off                 */
-#define Tx_EnUnder             0x00000100 /* 1:Enable Underrun               */
-#define Tx_EnExDefer           0x00000200 /* 1:Enable Excessive Deferral     */
-#define Tx_EnLCarr             0x00000400 /* 1:Enable Lost Carrier           */
-#define Tx_EnExColl            0x00000800 /* 1:Enable Excessive Collision    */
-#define Tx_EnLateColl          0x00001000 /* 1:Enable Late Collision         */
-#define Tx_EnTxPar             0x00002000 /* 1:Enable Transmit Parity        */
-#define Tx_EnComp              0x00004000 /* 1:Enable Completion             */
+#define Tx_En		       0x00000001 /* 1:Transmit enable		     */
+#define Tx_TxHalt	       0x00000002 /* 1:Transmit Halt Request	     */
+#define Tx_NoPad	       0x00000004 /* 1:Suppress Padding		     */
+#define Tx_NoCRC	       0x00000008 /* 1:Suppress Padding		     */
+#define Tx_FBack	       0x00000010 /* 1:Fast Back-off		     */
+#define Tx_EnUnder	       0x00000100 /* 1:Enable Underrun		     */
+#define Tx_EnExDefer	       0x00000200 /* 1:Enable Excessive Deferral     */
+#define Tx_EnLCarr	       0x00000400 /* 1:Enable Lost Carrier	     */
+#define Tx_EnExColl	       0x00000800 /* 1:Enable Excessive Collision    */
+#define Tx_EnLateColl	       0x00001000 /* 1:Enable Late Collision	     */
+#define Tx_EnTxPar	       0x00002000 /* 1:Enable Transmit Parity	     */
+#define Tx_EnComp	       0x00004000 /* 1:Enable Completion	     */
 
 /* Tx_Stat bit asign ------------------------------------------------------- */
-#define Tx_TxColl_MASK         0x0000000F /* Tx Collision Count              */
-#define Tx_ExColl              0x00000010 /* Excessive Collision             */
-#define Tx_TXDefer             0x00000020 /* Transmit Defered                */
-#define Tx_Paused              0x00000040 /* Transmit Paused                 */
-#define Tx_IntTx               0x00000080 /* Interrupt on Tx                 */
-#define Tx_Under               0x00000100 /* Underrun                        */
-#define Tx_Defer               0x00000200 /* Deferral                        */
-#define Tx_NCarr               0x00000400 /* No Carrier                      */
-#define Tx_10Stat              0x00000800 /* 10Mbps Status                   */
-#define Tx_LateColl            0x00001000 /* Late Collision                  */
-#define Tx_TxPar               0x00002000 /* Tx Parity Error                 */
-#define Tx_Comp                0x00004000 /* Completion                      */
-#define Tx_Halted              0x00008000 /* Tx Halted                       */
-#define Tx_SQErr               0x00010000 /* Signal Quality Error(SQE)       */
+#define Tx_TxColl_MASK	       0x0000000F /* Tx Collision Count		     */
+#define Tx_ExColl	       0x00000010 /* Excessive Collision	     */
+#define Tx_TXDefer	       0x00000020 /* Transmit Defered		     */
+#define Tx_Paused	       0x00000040 /* Transmit Paused		     */
+#define Tx_IntTx	       0x00000080 /* Interrupt on Tx		     */
+#define Tx_Under	       0x00000100 /* Underrun			     */
+#define Tx_Defer	       0x00000200 /* Deferral			     */
+#define Tx_NCarr	       0x00000400 /* No Carrier			     */
+#define Tx_10Stat	       0x00000800 /* 10Mbps Status		     */
+#define Tx_LateColl	       0x00001000 /* Late Collision		     */
+#define Tx_TxPar	       0x00002000 /* Tx Parity Error		     */
+#define Tx_Comp		       0x00004000 /* Completion			     */
+#define Tx_Halted	       0x00008000 /* Tx Halted			     */
+#define Tx_SQErr	       0x00010000 /* Signal Quality Error(SQE)	     */
 
 /* Rx_Ctl bit asign -------------------------------------------------------- */
-#define Rx_EnGood              0x00004000 /* 1:Enable Good                   */
-#define Rx_EnRxPar             0x00002000 /* 1:Enable Receive Parity         */
-#define Rx_EnLongErr           0x00000800 /* 1:Enable Long Error             */
-#define Rx_EnOver              0x00000400 /* 1:Enable OverFlow               */
-#define Rx_EnCRCErr            0x00000200 /* 1:Enable CRC Error              */
-#define Rx_EnAlign             0x00000100 /* 1:Enable Alignment              */
-#define Rx_IgnoreCRC           0x00000040 /* 1:Ignore CRC Value              */
-#define Rx_StripCRC            0x00000010 /* 1:Strip CRC Value               */
-#define Rx_ShortEn             0x00000008 /* 1:Short Enable                  */
-#define Rx_LongEn              0x00000004 /* 1:Long Enable                   */
-#define Rx_RxHalt              0x00000002 /* 1:Receive Halt Request          */
-#define Rx_RxEn                0x00000001 /* 1:Receive Intrrupt Enable       */
+#define Rx_EnGood	       0x00004000 /* 1:Enable Good		     */
+#define Rx_EnRxPar	       0x00002000 /* 1:Enable Receive Parity	     */
+#define Rx_EnLongErr	       0x00000800 /* 1:Enable Long Error	     */
+#define Rx_EnOver	       0x00000400 /* 1:Enable OverFlow		     */
+#define Rx_EnCRCErr	       0x00000200 /* 1:Enable CRC Error		     */
+#define Rx_EnAlign	       0x00000100 /* 1:Enable Alignment		     */
+#define Rx_IgnoreCRC	       0x00000040 /* 1:Ignore CRC Value		     */
+#define Rx_StripCRC	       0x00000010 /* 1:Strip CRC Value		     */
+#define Rx_ShortEn	       0x00000008 /* 1:Short Enable		     */
+#define Rx_LongEn	       0x00000004 /* 1:Long Enable		     */
+#define Rx_RxHalt	       0x00000002 /* 1:Receive Halt Request	     */
+#define Rx_RxEn		       0x00000001 /* 1:Receive Intrrupt Enable	     */
 
 /* Rx_Stat bit asign ------------------------------------------------------- */
-#define Rx_Halted              0x00008000 /* Rx Halted                       */
-#define Rx_Good                0x00004000 /* Rx Good                         */
-#define Rx_RxPar               0x00002000 /* Rx Parity Error                 */
-                            /* 0x00001000    not use                         */
-#define Rx_LongErr             0x00000800 /* Rx Long Error                   */
-#define Rx_Over                0x00000400 /* Rx Overflow                     */
-#define Rx_CRCErr              0x00000200 /* Rx CRC Error                    */
-#define Rx_Align               0x00000100 /* Rx Alignment Error              */
-#define Rx_10Stat              0x00000080 /* Rx 10Mbps Status                */
-#define Rx_IntRx               0x00000040 /* Rx Interrupt                    */
-#define Rx_CtlRecd             0x00000020 /* Rx Control Receive              */
-
-#define Rx_Stat_Mask           0x0000EFC0 /* Rx All Status Mask              */
+#define Rx_Halted	       0x00008000 /* Rx Halted			     */
+#define Rx_Good		       0x00004000 /* Rx Good			     */
+#define Rx_RxPar	       0x00002000 /* Rx Parity Error		     */
+			    /* 0x00001000    not use			     */
+#define Rx_LongErr	       0x00000800 /* Rx Long Error		     */
+#define Rx_Over		       0x00000400 /* Rx Overflow		     */
+#define Rx_CRCErr	       0x00000200 /* Rx CRC Error		     */
+#define Rx_Align	       0x00000100 /* Rx Alignment Error		     */
+#define Rx_10Stat	       0x00000080 /* Rx 10Mbps Status		     */
+#define Rx_IntRx	       0x00000040 /* Rx Interrupt		     */
+#define Rx_CtlRecd	       0x00000020 /* Rx Control Receive		     */
+
+#define Rx_Stat_Mask	       0x0000EFC0 /* Rx All Status Mask		     */
 
 /* Int_En bit asign -------------------------------------------------------- */
-#define Int_NRAbtEn            0x00000800 /* 1:Non-recoverable Abort Enable  */
-#define Int_TxCtlCmpEn         0x00000400 /* 1:Transmit Control Complete Enable */
-#define Int_DmParErrEn         0x00000200 /* 1:DMA Parity Error Enable       */
-#define Int_DParDEn            0x00000100 /* 1:Data Parity Error Enable      */
-#define Int_EarNotEn           0x00000080 /* 1:Early Notify Enable           */
-#define Int_DParErrEn          0x00000040 /* 1:Detected Parity Error Enable  */
-#define Int_SSysErrEn          0x00000020 /* 1:Signalled System Error Enable */
-#define Int_RMasAbtEn          0x00000010 /* 1:Received Master Abort Enable  */
-#define Int_RTargAbtEn         0x00000008 /* 1:Received Target Abort Enable  */
-#define Int_STargAbtEn         0x00000004 /* 1:Signalled Target Abort Enable */
-#define Int_BLExEn             0x00000002 /* 1:Buffer List Exhausted Enable  */
-#define Int_FDAExEn            0x00000001 /* 1:Free Descriptor Area          */
-                                          /*               Exhausted Enable  */
+#define Int_NRAbtEn	       0x00000800 /* 1:Non-recoverable Abort Enable  */
+#define Int_TxCtlCmpEn	       0x00000400 /* 1:Transmit Ctl Complete Enable  */
+#define Int_DmParErrEn	       0x00000200 /* 1:DMA Parity Error Enable	     */
+#define Int_DParDEn	       0x00000100 /* 1:Data Parity Error Enable	     */
+#define Int_EarNotEn	       0x00000080 /* 1:Early Notify Enable	     */
+#define Int_DParErrEn	       0x00000040 /* 1:Detected Parity Error Enable  */
+#define Int_SSysErrEn	       0x00000020 /* 1:Signalled System Error Enable */
+#define Int_RMasAbtEn	       0x00000010 /* 1:Received Master Abort Enable  */
+#define Int_RTargAbtEn	       0x00000008 /* 1:Received Target Abort Enable  */
+#define Int_STargAbtEn	       0x00000004 /* 1:Signalled Target Abort Enable */
+#define Int_BLExEn	       0x00000002 /* 1:Buffer List Exhausted Enable  */
+#define Int_FDAExEn	       0x00000001 /* 1:Free Descriptor Area	     */
+					  /*		   Exhausted Enable  */
 
 /* Int_Src bit asign ------------------------------------------------------- */
-#define Int_NRabt              0x00004000 /* 1:Non Recoverable error         */
-#define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear      */
-#define Int_BLEx               0x00001000 /* 1:Buffer List Empty & Clear     */
-#define Int_FDAEx              0x00000800 /* 1:FDA Empty & Clear             */
-#define Int_IntNRAbt           0x00000400 /* 1:Non Recoverable Abort         */
-#define	Int_IntCmp             0x00000200 /* 1:MAC control packet complete   */
-#define Int_IntExBD            0x00000100 /* 1:Interrupt Extra BD & Clear    */
-#define Int_DmParErr           0x00000080 /* 1:DMA Parity Error & Clear      */
-#define Int_IntEarNot          0x00000040 /* 1:Receive Data write & Clear    */
-#define Int_SWInt              0x00000020 /* 1:Software request & Clear      */
-#define Int_IntBLEx            0x00000010 /* 1:Buffer List Empty & Clear     */
-#define Int_IntFDAEx           0x00000008 /* 1:FDA Empty & Clear             */
-#define Int_IntPCI             0x00000004 /* 1:PCI controller & Clear        */
-#define Int_IntMacRx           0x00000002 /* 1:Rx controller & Clear         */
-#define Int_IntMacTx           0x00000001 /* 1:Tx controller & Clear         */
+#define Int_NRabt	       0x00004000 /* 1:Non Recoverable error	     */
+#define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear	     */
+#define Int_BLEx	       0x00001000 /* 1:Buffer List Empty & Clear     */
+#define Int_FDAEx	       0x00000800 /* 1:FDA Empty & Clear	     */
+#define Int_IntNRAbt	       0x00000400 /* 1:Non Recoverable Abort	     */
+#define Int_IntCmp	       0x00000200 /* 1:MAC control packet complete   */
+#define Int_IntExBD	       0x00000100 /* 1:Interrupt Extra BD & Clear    */
+#define Int_DmParErr	       0x00000080 /* 1:DMA Parity Error & Clear	     */
+#define Int_IntEarNot	       0x00000040 /* 1:Receive Data write & Clear    */
+#define Int_SWInt	       0x00000020 /* 1:Software request & Clear	     */
+#define Int_IntBLEx	       0x00000010 /* 1:Buffer List Empty & Clear     */
+#define Int_IntFDAEx	       0x00000008 /* 1:FDA Empty & Clear	     */
+#define Int_IntPCI	       0x00000004 /* 1:PCI controller & Clear	     */
+#define Int_IntMacRx	       0x00000002 /* 1:Rx controller & Clear	     */
+#define Int_IntMacTx	       0x00000001 /* 1:Tx controller & Clear	     */
 
 /* MD_CA bit asign --------------------------------------------------------- */
-#define MD_CA_PreSup           0x00001000 /* 1:Preamble Supress              */
-#define MD_CA_Busy             0x00000800 /* 1:Busy (Start Operation)        */
-#define MD_CA_Wr               0x00000400 /* 1:Write 0:Read                  */
+#define MD_CA_PreSup	       0x00001000 /* 1:Preamble Supress		     */
+#define MD_CA_Busy	       0x00000800 /* 1:Busy (Start Operation)	     */
+#define MD_CA_Wr	       0x00000400 /* 1:Write 0:Read		     */
 
 
 /*
@@ -307,24 +306,24 @@ struct BDesc {
 #define FD_ALIGN	16
 
 /* Frame Descripter bit asign ---------------------------------------------- */
-#define FD_FDLength_MASK       0x0000FFFF /* Length MASK                     */
-#define FD_BDCnt_MASK          0x001F0000 /* BD count MASK in FD             */
-#define FD_FrmOpt_MASK         0x7C000000 /* Frame option MASK               */
+#define FD_FDLength_MASK       0x0000FFFF /* Length MASK		     */
+#define FD_BDCnt_MASK	       0x001F0000 /* BD count MASK in FD	     */
+#define FD_FrmOpt_MASK	       0x7C000000 /* Frame option MASK		     */
 #define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
-#define FD_FrmOpt_IntTx        0x20000000 /* Tx only */
-#define FD_FrmOpt_NoCRC        0x10000000 /* Tx only */
+#define FD_FrmOpt_IntTx	       0x20000000 /* Tx only */
+#define FD_FrmOpt_NoCRC	       0x10000000 /* Tx only */
 #define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
 #define FD_FrmOpt_Packing      0x04000000 /* Rx only */
-#define FD_CownsFD             0x80000000 /* FD Controller owner bit         */
-#define FD_Next_EOL            0x00000001 /* FD EOL indicator                */
-#define FD_BDCnt_SHIFT         16
+#define FD_CownsFD	       0x80000000 /* FD Controller owner bit	     */
+#define FD_Next_EOL	       0x00000001 /* FD EOL indicator		     */
+#define FD_BDCnt_SHIFT	       16
 
 /* Buffer Descripter bit asign --------------------------------------------- */
-#define BD_BuffLength_MASK     0x0000FFFF /* Recieve Data Size               */
-#define BD_RxBDID_MASK         0x00FF0000 /* BD ID Number MASK               */
-#define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number           */
-#define BD_CownsBD             0x80000000 /* BD Controller owner bit         */
-#define BD_RxBDID_SHIFT        16
+#define BD_BuffLength_MASK     0x0000FFFF /* Recieve Data Size		     */
+#define BD_RxBDID_MASK	       0x00FF0000 /* BD ID Number MASK		     */
+#define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number	     */
+#define BD_CownsBD	       0x80000000 /* BD Controller owner bit	     */
+#define BD_RxBDID_SHIFT	       16
 #define BD_RxBDSeqN_SHIFT      24
 
 
@@ -348,13 +347,15 @@ struct BDesc {
 	Int_STargAbtEn | \
 	Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
 #define DMA_CTL_CMD	DMA_BURST_SIZE
-#define HAVE_DMA_RXALIGN(lp)	likely((lp)->boardtype != TC35815CF)
+#define HAVE_DMA_RXALIGN(lp)	likely((lp)->chiptype != TC35815CF)
 
 /* Tuning parameters */
 #define DMA_BURST_SIZE	32
 #define TX_THRESHOLD	1024
-#define TX_THRESHOLD_MAX 1536       /* used threshold with packet max byte for low pci transfer ability.*/
-#define TX_THRESHOLD_KEEP_LIMIT 10  /* setting threshold max value when overrun error occured this count. */
+/* used threshold with packet max byte for low pci transfer ability.*/
+#define TX_THRESHOLD_MAX 1536
+/* setting threshold max value when overrun error occured this count. */
+#define TX_THRESHOLD_KEEP_LIMIT 10
 
 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
 #ifdef TC35815_USE_PACKEDBUFFER
@@ -396,21 +397,12 @@ struct FrFD {
 };
 
 
-#define tc_readl(addr)	readl(addr)
-#define tc_writel(d, addr)	writel(d, addr)
+#define tc_readl(addr)	ioread32(addr)
+#define tc_writel(d, addr)	iowrite32(d, addr)
 
 #define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)
 
-/* Timer state engine. */
-enum tc35815_timer_state {
-	arbwait  = 0,	/* Waiting for auto negotiation to complete.          */
-	lupwait  = 1,	/* Auto-neg complete, awaiting link-up status.        */
-	ltrywait = 2,	/* Forcing try of all modes, from fastest to slowest. */
-	asleep   = 3,	/* Time inactive.                                     */
-	lcheck   = 4,	/* Check link status.                                 */
-};
-
-/* Information that need to be kept for each board. */
+/* Information that need to be kept for each controller. */
 struct tc35815_local {
 	struct pci_dev *pci_dev;
 
@@ -418,12 +410,11 @@ struct tc35815_local {
 	struct napi_struct napi;
 
 	/* statistics */
-	struct net_device_stats stats;
 	struct {
 		int max_tx_qlen;
 		int tx_ints;
 		int rx_ints;
-	        int tx_underrun;
+		int tx_underrun;
 	} lstats;
 
 	/* Tx control lock.  This protects the transmit buffer ring
@@ -433,12 +424,12 @@ struct tc35815_local {
 	 */
 	spinlock_t lock;
 
-	int phy_addr;
-	int fullduplex;
-	unsigned short saved_lpa;
-	struct timer_list timer;
-	enum tc35815_timer_state timer_state; /* State of auto-neg timer. */
-	unsigned int timer_ticks;	/* Number of clicks at each state  */
+	struct mii_bus mii_bus;
+	struct phy_device *phy_dev;
+	int duplex;
+	int speed;
+	int link;
+	struct work_struct restart_work;
 
 	/*
 	 * Transmitting: Batch Mode.
@@ -452,7 +443,7 @@ struct tc35815_local {
 	 *	RX_BUF_NUM BD in Free Buffer FD.
 	 *	One Free Buffer BD has ETH_FRAME_LEN data buffer.
 	 */
-	void * fd_buf;	/* for TxFD, RxFD, FrFD */
+	void *fd_buf;	/* for TxFD, RxFD, FrFD */
 	dma_addr_t fd_buf_dma;
 	struct TxFD *tfd_base;
 	unsigned int tfd_start;
@@ -463,7 +454,7 @@ struct tc35815_local {
 	struct FrFD *fbl_ptr;
 #ifdef TC35815_USE_PACKEDBUFFER
 	unsigned char fbl_curid;
-	void * data_buf[RX_BUF_NUM];		/* packing */
+	void *data_buf[RX_BUF_NUM];		/* packing */
 	dma_addr_t data_buf_dma[RX_BUF_NUM];
 	struct {
 		struct sk_buff *skb;
@@ -476,10 +467,8 @@ struct tc35815_local {
 		dma_addr_t skb_dma;
 	} tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
 #endif
-	struct mii_if_info mii;
-	unsigned short mii_id[2];
 	u32 msg_enable;
-	board_t boardtype;
+	enum tc35815_chiptype chiptype;
 };
 
 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
@@ -506,13 +495,14 @@ static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
 }
 
 #define TC35815_DMA_SYNC_ONDEMAND
-static void* alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
+static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
 {
 #ifdef TC35815_DMA_SYNC_ONDEMAND
 	void *buf;
 	/* pci_map + pci_dma_sync will be more effective than
 	 * pci_alloc_consistent on some archs. */
-	if ((buf = (void *)__get_free_page(GFP_ATOMIC)) == NULL)
+	buf = (void *)__get_free_page(GFP_ATOMIC);
+	if (!buf)
 		return NULL;
 	*dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
 				     PCI_DMA_FROMDEVICE);
@@ -577,7 +567,7 @@ static void	tc35815_txdone(struct net_device *dev);
 static int	tc35815_close(struct net_device *dev);
 static struct	net_device_stats *tc35815_get_stats(struct net_device *dev);
 static void	tc35815_set_multicast_list(struct net_device *dev);
-static void     tc35815_tx_timeout(struct net_device *dev);
+static void	tc35815_tx_timeout(struct net_device *dev);
 static int	tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void	tc35815_poll_controller(struct net_device *dev);
@@ -585,21 +575,225 @@ static void	tc35815_poll_controller(struct net_device *dev);
 static const struct ethtool_ops tc35815_ethtool_ops;
 
 /* Example routines you must write ;->. */
-static void 	tc35815_chip_reset(struct net_device *dev);
-static void 	tc35815_chip_init(struct net_device *dev);
-static void	tc35815_find_phy(struct net_device *dev);
-static void 	tc35815_phy_chip_init(struct net_device *dev);
+static void	tc35815_chip_reset(struct net_device *dev);
+static void	tc35815_chip_init(struct net_device *dev);
 
 #ifdef DEBUG
 static void	panic_queues(struct net_device *dev);
 #endif
 
-static void tc35815_timer(unsigned long data);
-static void tc35815_start_auto_negotiation(struct net_device *dev,
-					   struct ethtool_cmd *ep);
-static int tc_mdio_read(struct net_device *dev, int phy_id, int location);
-static void tc_mdio_write(struct net_device *dev, int phy_id, int location,
-			  int val);
+static void tc35815_restart_work(struct work_struct *work);
+
+static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct net_device *dev = bus->priv;
+	struct tc35815_regs __iomem *tr =
+		(struct tc35815_regs __iomem *)dev->base_addr;
+	unsigned long timeout = jiffies + 10;
+
+	tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
+	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+	return tc_readl(&tr->MD_Data) & 0xffff;
+}
+
+static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
+{
+	struct net_device *dev = bus->priv;
+	struct tc35815_regs __iomem *tr =
+		(struct tc35815_regs __iomem *)dev->base_addr;
+	unsigned long timeout = jiffies + 10;
+
+	tc_writel(val, &tr->MD_Data);
+	tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
+		  &tr->MD_CA);
+	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+	return 0;
+}
+
+static void tc_handle_link_change(struct net_device *dev)
+{
+	struct tc35815_local *lp = netdev_priv(dev);
+	struct phy_device *phydev = lp->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	spin_lock_irqsave(&lp->lock, flags);
+	if (phydev->link &&
+	    (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
+		struct tc35815_regs __iomem *tr =
+			(struct tc35815_regs __iomem *)dev->base_addr;
+		u32 reg;
+
+		reg = tc_readl(&tr->MAC_Ctl);
+		reg |= MAC_HaltReq;
+		tc_writel(reg, &tr->MAC_Ctl);
+		if (phydev->duplex == DUPLEX_FULL)
+			reg |= MAC_FullDup;
+		else
+			reg &= ~MAC_FullDup;
+		tc_writel(reg, &tr->MAC_Ctl);
+		reg &= ~MAC_HaltReq;
+		tc_writel(reg, &tr->MAC_Ctl);
+
+		/*
+		 * TX4939 PCFG.SPEEDn bit will be changed on
+		 * NETDEV_CHANGE event.
+		 */
+
+#if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
+		/*
+		 * WORKAROUND: enable LostCrS only if half duplex
+		 * operation.
+		 * (TX4939 does not have EnLCarr)
+		 */
+		if (phydev->duplex == DUPLEX_HALF &&
+		    lp->chiptype != TC35815_TX4939)
+			tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
+				  &tr->Tx_Ctl);
+#endif
+
+		lp->speed = phydev->speed;
+		lp->duplex = phydev->duplex;
+		status_change = 1;
+	}
+
+	if (phydev->link != lp->link) {
+		if (phydev->link) {
+#ifdef WORKAROUND_100HALF_PROMISC
+			/* delayed promiscuous enabling */
+			if (dev->flags & IFF_PROMISC)
+				tc35815_set_multicast_list(dev);
+#endif
+			netif_schedule(dev);
+		} else {
+			lp->speed = 0;
+			lp->duplex = -1;
+		}
+		lp->link = phydev->link;
+
+		status_change = 1;
+	}
+	spin_unlock_irqrestore(&lp->lock, flags);
+
+	if (status_change && netif_msg_link(lp)) {
+		phy_print_status(phydev);
+#ifdef DEBUG
+		printk(KERN_DEBUG
+		       "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
+		       dev->name,
+		       phy_read(phydev, MII_BMCR),
+		       phy_read(phydev, MII_BMSR),
+		       phy_read(phydev, MII_LPA));
+#endif
+	}
+}
+
+static int tc_mii_probe(struct net_device *dev)
+{
+	struct tc35815_local *lp = netdev_priv(dev);
+	struct phy_device *phydev = NULL;
+	int phy_addr;
+	u32 dropmask;
+
+	/* find the first phy */
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (lp->mii_bus.phy_map[phy_addr]) {
+			if (phydev) {
+				printk(KERN_ERR "%s: multiple PHYs found\n",
+				       dev->name);
+				return -EINVAL;
+			}
+			phydev = lp->mii_bus.phy_map[phy_addr];
+			break;
+		}
+	}
+
+	if (!phydev) {
+		printk(KERN_ERR "%s: no PHY found\n", dev->name);
+		return -ENODEV;
+	}
+
+	/* attach the mac to the phy */
+	phydev = phy_connect(dev, phydev->dev.bus_id,
+			     &tc_handle_link_change, 0,
+			     lp->chiptype == TC35815_TX4939 ?
+			     PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
+	if (IS_ERR(phydev)) {
+		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+		return PTR_ERR(phydev);
+	}
+	printk(KERN_INFO "%s: attached PHY driver [%s] "
+		"(mii_bus:phy_addr=%s, id=%x)\n",
+		dev->name, phydev->drv->name, phydev->dev.bus_id,
+		phydev->phy_id);
+
+	/* mask with MAC supported features */
+	phydev->supported &= PHY_BASIC_FEATURES;
+	dropmask = 0;
+	if (options.speed == 10)
+		dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
+	else if (options.speed == 100)
+		dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
+	if (options.duplex == 1)
+		dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
+	else if (options.duplex == 2)
+		dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
+	phydev->supported &= ~dropmask;
+	phydev->advertising = phydev->supported;
+
+	lp->link = 0;
+	lp->speed = 0;
+	lp->duplex = -1;
+	lp->phy_dev = phydev;
+
+	return 0;
+}
+
+static int tc_mii_init(struct net_device *dev)
+{
+	struct tc35815_local *lp = netdev_priv(dev);
+	int err;
+	int i;
+
+	lp->mii_bus.name = "tc35815_mii_bus";
+	lp->mii_bus.read = tc_mdio_read;
+	lp->mii_bus.write = tc_mdio_write;
+	snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "%x",
+		 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
+	lp->mii_bus.priv = dev;
+	lp->mii_bus.dev = &lp->pci_dev->dev;
+	lp->mii_bus.irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!lp->mii_bus.irq) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		lp->mii_bus.irq[i] = PHY_POLL;
+
+	err = mdiobus_register(&lp->mii_bus);
+	if (err)
+		goto err_out_free_mdio_irq;
+	err = tc_mii_probe(dev);
+	if (err)
+		goto err_out_unregister_bus;
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(&lp->mii_bus);
+err_out_free_mdio_irq:
+	kfree(lp->mii_bus.irq);
+err_out:
+	return err;
+}
 
 #ifdef CONFIG_CPU_TX49XX
 /*
@@ -617,7 +811,7 @@ static int __devinit tc35815_mac_match(struct device *dev, void *data)
 
 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
 {
-	struct tc35815_local *lp = dev->priv;
+	struct tc35815_local *lp = netdev_priv(dev);
 	struct device *pd = bus_find_device(&platform_bus_type, NULL,
 					    lp->pci_dev, tc35815_mac_match);
 	if (pd) {
@@ -635,7 +829,7 @@ static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
 }
 #endif
 
-static int __devinit tc35815_init_dev_addr (struct net_device *dev)
+static int __devinit tc35815_init_dev_addr(struct net_device *dev)
 {
 	struct tc35815_regs __iomem *tr =
 		(struct tc35815_regs __iomem *)dev->base_addr;
@@ -657,21 +851,21 @@ static int __devinit tc35815_init_dev_addr (struct net_device *dev)
 	return 0;
 }
 
-static int __devinit tc35815_init_one (struct pci_dev *pdev,
-				       const struct pci_device_id *ent)
+static int __devinit tc35815_init_one(struct pci_dev *pdev,
+				      const struct pci_device_id *ent)
 {
 	void __iomem *ioaddr = NULL;
 	struct net_device *dev;
 	struct tc35815_local *lp;
 	int rc;
-	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
+	DECLARE_MAC_BUF(mac);
 
 	static int printed_version;
 	if (!printed_version++) {
 		printk(version);