cassini/niu/sun*: Move the Sun drivers

Moves the Sun drivers into drivers/net/ethernet/sun/ and make
the necessary Kconfig and Makefile changes.

Oliver Hartkopp <socketcan@hartkopp.net> suggested removing the
sun* prefix on the driver names.  This type of change I will
leave up to the driver maintainers.

CC: Sam Creasey <sammy@sammy.net>
CC: Adrian Sun <asun@darksunrising.com>
CC: Benjamin Herrenscmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 0 insertions, 3306 deletions

diff --git a/drivers/net/niu.h b/drivers/net/niu.h
deleted file mode 100644
index 51e177e1860..00000000000
--- a/drivers/net/niu.h
+++ /dev/null
@@ -1,3306 +0,0 @@
-/* niu.h: Definitions for Neptune ethernet driver.
- *
- * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _NIU_H
-#define _NIU_H
-
-#define PIO			0x000000UL
-#define FZC_PIO			0x080000UL
-#define FZC_MAC			0x180000UL
-#define FZC_IPP			0x280000UL
-#define FFLP			0x300000UL
-#define FZC_FFLP		0x380000UL
-#define PIO_VADDR		0x400000UL
-#define ZCP			0x500000UL
-#define FZC_ZCP			0x580000UL
-#define DMC			0x600000UL
-#define FZC_DMC			0x680000UL
-#define TXC			0x700000UL
-#define FZC_TXC			0x780000UL
-#define PIO_LDSV		0x800000UL
-#define PIO_PIO_LDGIM		0x900000UL
-#define PIO_IMASK0		0xa00000UL
-#define PIO_IMASK1		0xb00000UL
-#define FZC_PROM		0xc80000UL
-#define FZC_PIM			0xd80000UL
-
-#define LDSV0(LDG)		(PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
-#define LDSV1(LDG)		(PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
-#define LDSV2(LDG)		(PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)
-
-#define LDG_IMGMT(LDG)		(PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
-#define  LDG_IMGMT_ARM		0x0000000080000000ULL
-#define  LDG_IMGMT_TIMER	0x000000000000003fULL
-
-#define LD_IM0(IDX)		(PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
-#define  LD_IM0_MASK		0x0000000000000003ULL
-
-#define LD_IM1(IDX)		(PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
-#define  LD_IM1_MASK		0x0000000000000003ULL
-
-#define LDG_TIMER_RES		(FZC_PIO + 0x00008UL)
-#define  LDG_TIMER_RES_VAL	0x00000000000fffffULL
-
-#define DIRTY_TID_CTL		(FZC_PIO + 0x00010UL)
-#define  DIRTY_TID_CTL_NPTHRED	0x00000000003f0000ULL
-#define  DIRTY_TID_CTL_RDTHRED	0x00000000000003f0ULL
-#define  DIRTY_TID_CTL_DTIDCLR	0x0000000000000002ULL
-#define  DIRTY_TID_CTL_DTIDENAB	0x0000000000000001ULL
-
-#define DIRTY_TID_STAT		(FZC_PIO + 0x00018UL)
-#define  DIRTY_TID_STAT_NPWSTAT	0x0000000000003f00ULL
-#define  DIRTY_TID_STAT_RDSTAT	0x000000000000003fULL
-
-#define RST_CTL			(FZC_PIO + 0x00038UL)
-#define  RST_CTL_MAC_RST3	0x0000000000400000ULL
-#define  RST_CTL_MAC_RST2	0x0000000000200000ULL
-#define  RST_CTL_MAC_RST1	0x0000000000100000ULL
-#define  RST_CTL_MAC_RST0	0x0000000000080000ULL
-#define  RST_CTL_ACK_TO_EN	0x0000000000000800ULL
-#define  RST_CTL_ACK_TO_VAL	0x00000000000007feULL
-
-#define SMX_CFIG_DAT		(FZC_PIO + 0x00040UL)
-#define  SMX_CFIG_DAT_RAS_DET	0x0000000080000000ULL
-#define  SMX_CFIG_DAT_RAS_INJ	0x0000000040000000ULL
-#define  SMX_CFIG_DAT_XACT_TO	0x000000000fffffffULL
-
-#define SMX_INT_STAT		(FZC_PIO + 0x00048UL)
-#define  SMX_INT_STAT_STAT	0x00000000ffffffffULL
-
-#define SMX_CTL			(FZC_PIO + 0x00050UL)
-#define  SMX_CTL_CTL		0x00000000ffffffffULL
-
-#define SMX_DBG_VEC		(FZC_PIO + 0x00058UL)
-#define  SMX_DBG_VEC_VEC	0x00000000ffffffffULL
-
-#define PIO_DBG_SEL		(FZC_PIO + 0x00060UL)
-#define  PIO_DBG_SEL_SEL	0x000000000000003fULL
-
-#define PIO_TRAIN_VEC		(FZC_PIO + 0x00068UL)
-#define  PIO_TRAIN_VEC_VEC	0x00000000ffffffffULL
-
-#define PIO_ARB_CTL		(FZC_PIO + 0x00070UL)
-#define  PIO_ARB_CTL_CTL	0x00000000ffffffffULL
-
-#define PIO_ARB_DBG_VEC		(FZC_PIO + 0x00078UL)
-#define  PIO_ARB_DBG_VEC_VEC	0x00000000ffffffffULL
-
-#define SYS_ERR_MASK		(FZC_PIO + 0x00090UL)
-#define  SYS_ERR_MASK_META2	0x0000000000000400ULL
-#define  SYS_ERR_MASK_META1	0x0000000000000200ULL
-#define  SYS_ERR_MASK_PEU	0x0000000000000100ULL
-#define  SYS_ERR_MASK_TXC	0x0000000000000080ULL
-#define  SYS_ERR_MASK_RDMC	0x0000000000000040ULL
-#define  SYS_ERR_MASK_TDMC	0x0000000000000020ULL
-#define  SYS_ERR_MASK_ZCP	0x0000000000000010ULL
-#define  SYS_ERR_MASK_FFLP	0x0000000000000008ULL
-#define  SYS_ERR_MASK_IPP	0x0000000000000004ULL
-#define  SYS_ERR_MASK_MAC	0x0000000000000002ULL
-#define  SYS_ERR_MASK_SMX	0x0000000000000001ULL
-
-#define SYS_ERR_STAT			(FZC_PIO + 0x00098UL)
-#define  SYS_ERR_STAT_META2		0x0000000000000400ULL
-#define  SYS_ERR_STAT_META1		0x0000000000000200ULL
-#define  SYS_ERR_STAT_PEU		0x0000000000000100ULL
-#define  SYS_ERR_STAT_TXC		0x0000000000000080ULL
-#define  SYS_ERR_STAT_RDMC		0x0000000000000040ULL
-#define  SYS_ERR_STAT_TDMC		0x0000000000000020ULL
-#define  SYS_ERR_STAT_ZCP		0x0000000000000010ULL
-#define  SYS_ERR_STAT_FFLP		0x0000000000000008ULL
-#define  SYS_ERR_STAT_IPP		0x0000000000000004ULL
-#define  SYS_ERR_STAT_MAC		0x0000000000000002ULL
-#define  SYS_ERR_STAT_SMX		0x0000000000000001ULL
-
-#define SID(LDG)			(FZC_PIO + 0x10200UL + (LDG) * 8UL)
-#define  SID_FUNC			0x0000000000000060ULL
-#define  SID_FUNC_SHIFT			5
-#define  SID_VECTOR			0x000000000000001fULL
-#define  SID_VECTOR_SHIFT		0
-
-#define LDG_NUM(LDN)			(FZC_PIO + 0x20000UL + (LDN) * 8UL)
-
-#define XMAC_PORT0_OFF			(FZC_MAC + 0x000000)
-#define XMAC_PORT1_OFF			(FZC_MAC + 0x006000)
-#define BMAC_PORT2_OFF			(FZC_MAC + 0x00c000)
-#define BMAC_PORT3_OFF			(FZC_MAC + 0x010000)
-
-/* XMAC registers, offset from np->mac_regs  */
-
-#define XTXMAC_SW_RST			0x00000UL
-#define  XTXMAC_SW_RST_REG_RS		0x0000000000000002ULL
-#define  XTXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL
-
-#define XRXMAC_SW_RST			0x00008UL
-#define  XRXMAC_SW_RST_REG_RS		0x0000000000000002ULL
-#define  XRXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL
-
-#define XTXMAC_STATUS			0x00020UL
-#define  XTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL
-#define  XTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
-#define  XTXMAC_STATUS_TXFIFO_XFR_ERR	0x0000000000000010ULL
-#define  XTXMAC_STATUS_TXMAC_OFLOW	0x0000000000000008ULL
-#define  XTXMAC_STATUS_MAX_PSIZE_ERR	0x0000000000000004ULL
-#define  XTXMAC_STATUS_TXMAC_UFLOW	0x0000000000000002ULL
-#define  XTXMAC_STATUS_FRAME_XMITED	0x0000000000000001ULL
-
-#define XRXMAC_STATUS			0x00028UL
-#define  XRXMAC_STATUS_RXHIST7_CNT_EXP	0x0000000000100000ULL
-#define  XRXMAC_STATUS_LCL_FLT_STATUS	0x0000000000080000ULL
-#define  XRXMAC_STATUS_RFLT_DET		0x0000000000040000ULL
-#define  XRXMAC_STATUS_LFLT_CNT_EXP	0x0000000000020000ULL
-#define  XRXMAC_STATUS_PHY_MDINT	0x0000000000010000ULL
-#define  XRXMAC_STATUS_ALIGNERR_CNT_EXP	0x0000000000010000ULL
-#define  XRXMAC_STATUS_RXFRAG_CNT_EXP	0x0000000000008000ULL
-#define  XRXMAC_STATUS_RXMULTF_CNT_EXP	0x0000000000004000ULL
-#define  XRXMAC_STATUS_RXBCAST_CNT_EXP	0x0000000000002000ULL
-#define  XRXMAC_STATUS_RXHIST6_CNT_EXP	0x0000000000001000ULL
-#define  XRXMAC_STATUS_RXHIST5_CNT_EXP	0x0000000000000800ULL
-#define  XRXMAC_STATUS_RXHIST4_CNT_EXP	0x0000000000000400ULL
-#define  XRXMAC_STATUS_RXHIST3_CNT_EXP	0x0000000000000200ULL
-#define  XRXMAC_STATUS_RXHIST2_CNT_EXP	0x0000000000000100ULL
-#define  XRXMAC_STATUS_RXHIST1_CNT_EXP	0x0000000000000080ULL
-#define  XRXMAC_STATUS_RXOCTET_CNT_EXP	0x0000000000000040ULL
-#define  XRXMAC_STATUS_CVIOLERR_CNT_EXP	0x0000000000000020ULL
-#define  XRXMAC_STATUS_LENERR_CNT_EXP	0x0000000000000010ULL
-#define  XRXMAC_STATUS_CRCERR_CNT_EXP	0x0000000000000008ULL
-#define  XRXMAC_STATUS_RXUFLOW		0x0000000000000004ULL
-#define  XRXMAC_STATUS_RXOFLOW		0x0000000000000002ULL
-#define  XRXMAC_STATUS_FRAME_RCVD	0x0000000000000001ULL
-
-#define XMAC_FC_STAT			0x00030UL
-#define  XMAC_FC_STAT_RX_RCV_PAUSE_TIME	0x00000000ffff0000ULL
-#define  XMAC_FC_STAT_TX_MAC_NPAUSE	0x0000000000000004ULL
-#define  XMAC_FC_STAT_TX_MAC_PAUSE	0x0000000000000002ULL
-#define  XMAC_FC_STAT_RX_MAC_RPAUSE	0x0000000000000001ULL
-
-#define XTXMAC_STAT_MSK			0x00040UL
-#define  XTXMAC_STAT_MSK_FRAME_CNT_EXP	0x0000000000000800ULL
-#define  XTXMAC_STAT_MSK_BYTE_CNT_EXP	0x0000000000000400ULL
-#define  XTXMAC_STAT_MSK_TXFIFO_XFR_ERR	0x0000000000000010ULL
-#define  XTXMAC_STAT_MSK_TXMAC_OFLOW	0x0000000000000008ULL
-#define  XTXMAC_STAT_MSK_MAX_PSIZE_ERR	0x0000000000000004ULL
-#define  XTXMAC_STAT_MSK_TXMAC_UFLOW	0x0000000000000002ULL
-#define  XTXMAC_STAT_MSK_FRAME_XMITED	0x0000000000000001ULL
-
-#define XRXMAC_STAT_MSK				0x00048UL
-#define  XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK	0x0000000000080000ULL
-#define  XRXMAC_STAT_MSK_RFLT_DET		0x0000000000040000ULL
-#define  XRXMAC_STAT_MSK_LFLT_CNT_EXP		0x0000000000020000ULL
-#define  XRXMAC_STAT_MSK_PHY_MDINT		0x0000000000010000ULL
-#define  XRXMAC_STAT_MSK_RXFRAG_CNT_EXP		0x0000000000008000ULL
-#define  XRXMAC_STAT_MSK_RXMULTF_CNT_EXP	0x0000000000004000ULL
-#define  XRXMAC_STAT_MSK_RXBCAST_CNT_EXP	0x0000000000002000ULL
-#define  XRXMAC_STAT_MSK_RXHIST6_CNT_EXP	0x0000000000001000ULL
-#define  XRXMAC_STAT_MSK_RXHIST5_CNT_EXP	0x0000000000000800ULL
-#define  XRXMAC_STAT_MSK_RXHIST4_CNT_EXP	0x0000000000000400ULL
-#define  XRXMAC_STAT_MSK_RXHIST3_CNT_EXP	0x0000000000000200ULL
-#define  XRXMAC_STAT_MSK_RXHIST2_CNT_EXP	0x0000000000000100ULL
-#define  XRXMAC_STAT_MSK_RXHIST1_CNT_EXP	0x0000000000000080ULL
-#define  XRXMAC_STAT_MSK_RXOCTET_CNT_EXP	0x0000000000000040ULL
-#define  XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP	0x0000000000000020ULL
-#define  XRXMAC_STAT_MSK_LENERR_CNT_EXP		0x0000000000000010ULL
-#define  XRXMAC_STAT_MSK_CRCERR_CNT_EXP		0x0000000000000008ULL
-#define  XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP	0x0000000000000004ULL
-#define  XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP	0x0000000000000002ULL
-#define  XRXMAC_STAT_MSK_FRAME_RCVD		0x0000000000000001ULL
-
-#define XMAC_FC_MSK			0x00050UL
-#define  XMAC_FC_MSK_TX_MAC_NPAUSE	0x0000000000000004ULL
-#define  XMAC_FC_MSK_TX_MAC_PAUSE	0x0000000000000002ULL
-#define  XMAC_FC_MSK_RX_MAC_RPAUSE	0x0000000000000001ULL
-
-#define XMAC_CONFIG			0x00060UL
-#define  XMAC_CONFIG_SEL_CLK_25MHZ	0x0000000080000000ULL
-#define  XMAC_CONFIG_1G_PCS_BYPASS	0x0000000040000000ULL
-#define  XMAC_CONFIG_10G_XPCS_BYPASS	0x0000000020000000ULL
-#define  XMAC_CONFIG_MODE_MASK		0x0000000018000000ULL
-#define  XMAC_CONFIG_MODE_XGMII		0x0000000000000000ULL
-#define  XMAC_CONFIG_MODE_GMII		0x0000000008000000ULL
-#define  XMAC_CONFIG_MODE_MII		0x0000000010000000ULL
-#define  XMAC_CONFIG_LFS_DISABLE	0x0000000004000000ULL
-#define  XMAC_CONFIG_LOOPBACK		0x0000000002000000ULL
-#define  XMAC_CONFIG_TX_OUTPUT_EN	0x0000000001000000ULL
-#define  XMAC_CONFIG_SEL_POR_CLK_SRC	0x0000000000800000ULL
-#define  XMAC_CONFIG_LED_POLARITY	0x0000000000400000ULL
-#define  XMAC_CONFIG_FORCE_LED_ON	0x0000000000200000ULL
-#define  XMAC_CONFIG_PASS_FLOW_CTRL	0x0000000000100000ULL
-#define  XMAC_CONFIG_RCV_PAUSE_ENABLE	0x0000000000080000ULL
-#define  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN	0x0000000000040000ULL
-#define  XMAC_CONFIG_STRIP_CRC		0x0000000000020000ULL
-#define  XMAC_CONFIG_ADDR_FILTER_EN	0x0000000000010000ULL
-#define  XMAC_CONFIG_HASH_FILTER_EN	0x0000000000008000ULL
-#define  XMAC_CONFIG_RX_CODEV_CHK_DIS	0x0000000000004000ULL
-#define  XMAC_CONFIG_RESERVED_MULTICAST	0x0000000000002000ULL
-#define  XMAC_CONFIG_RX_CRC_CHK_DIS	0x0000000000001000ULL
-#define  XMAC_CONFIG_ERR_CHK_DIS	0x0000000000000800ULL
-#define  XMAC_CONFIG_PROMISC_GROUP	0x0000000000000400ULL
-#define  XMAC_CONFIG_PROMISCUOUS	0x0000000000000200ULL
-#define  XMAC_CONFIG_RX_MAC_ENABLE	0x0000000000000100ULL
-#define  XMAC_CONFIG_WARNING_MSG_EN	0x0000000000000080ULL
-#define  XMAC_CONFIG_ALWAYS_NO_CRC	0x0000000000000008ULL
-#define  XMAC_CONFIG_VAR_MIN_IPG_EN	0x0000000000000004ULL
-#define  XMAC_CONFIG_STRETCH_MODE	0x0000000000000002ULL
-#define  XMAC_CONFIG_TX_ENABLE		0x0000000000000001ULL
-
-#define XMAC_IPG			0x00080UL
-#define  XMAC_IPG_STRETCH_CONST		0x0000000000e00000ULL
-#define  XMAC_IPG_STRETCH_CONST_SHIFT	21
-#define  XMAC_IPG_STRETCH_RATIO		0x00000000001f0000ULL
-#define  XMAC_IPG_STRETCH_RATIO_SHIFT	16
-#define  XMAC_IPG_IPG_MII_GMII		0x000000000000ff00ULL
-#define  XMAC_IPG_IPG_MII_GMII_SHIFT	8
-#define  XMAC_IPG_IPG_XGMII		0x0000000000000007ULL
-#define  XMAC_IPG_IPG_XGMII_SHIFT	0
-
-#define IPG_12_15_XGMII			3
-#define IPG_16_19_XGMII			4
-#define IPG_20_23_XGMII			5
-#define IPG_12_MII_GMII			10
-#define IPG_13_MII_GMII			11
-#define IPG_14_MII_GMII			12
-#define IPG_15_MII_GMII			13
-#define IPG_16_MII_GMII			14
-
-#define XMAC_MIN			0x00088UL
-#define  XMAC_MIN_RX_MIN_PKT_SIZE	0x000000003ff00000ULL
-#define  XMAC_MIN_RX_MIN_PKT_SIZE_SHFT	20
-#define  XMAC_MIN_SLOT_TIME		0x000000000003fc00ULL
-#define  XMAC_MIN_SLOT_TIME_SHFT	10
-#define  XMAC_MIN_TX_MIN_PKT_SIZE	0x00000000000003ffULL
-#define  XMAC_MIN_TX_MIN_PKT_SIZE_SHFT	0
-
-#define XMAC_MAX			0x00090UL
-#define  XMAC_MAX_FRAME_SIZE		0x0000000000003fffULL
-#define  XMAC_MAX_FRAME_SIZE_SHFT	0
-
-#define XMAC_ADDR0			0x000a0UL
-#define  XMAC_ADDR0_ADDR0		0x000000000000ffffULL
-
-#define XMAC_ADDR1			0x000a8UL
-#define  XMAC_ADDR1_ADDR1		0x000000000000ffffULL
-
-#define XMAC_ADDR2			0x000b0UL
-#define  XMAC_ADDR2_ADDR2		0x000000000000ffffULL
-
-#define XMAC_ADDR_CMPEN			0x00208UL
-#define  XMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
-#define  XMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
-#define  XMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
-#define  XMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
-#define  XMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
-#define  XMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
-#define  XMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
-#define  XMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
-#define  XMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
-#define  XMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
-#define  XMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
-#define  XMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
-#define  XMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
-#define  XMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
-#define  XMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
-#define  XMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL
-
-#define XMAC_NUM_ALT_ADDR		16
-
-#define XMAC_ALT_ADDR0(NUM)		(0x00218UL + (NUM)*0x18UL)
-#define  XMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL
-
-#define XMAC_ALT_ADDR1(NUM)		(0x00220UL + (NUM)*0x18UL)
-#define  XMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL
-
-#define XMAC_ALT_ADDR2(NUM)		(0x00228UL + (NUM)*0x18UL)
-#define  XMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL
-
-#define XMAC_ADD_FILT0			0x00818UL
-#define  XMAC_ADD_FILT0_FILT0		0x000000000000ffffULL
-
-#define XMAC_ADD_FILT1			0x00820UL
-#define  XMAC_ADD_FILT1_FILT1		0x000000000000ffffULL
-
-#define XMAC_ADD_FILT2			0x00828UL
-#define  XMAC_ADD_FILT2_FILT2		0x000000000000ffffULL
-
-#define XMAC_ADD_FILT12_MASK		0x00830UL
-#define  XMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL
-
-#define XMAC_ADD_FILT00_MASK		0x00838UL
-#define  XMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL
-
-#define XMAC_HASH_TBL(NUM)		(0x00840UL + (NUM) * 0x8UL)
-#define XMAC_HASH_TBL_VAL		0x000000000000ffffULL
-
-#define XMAC_NUM_HOST_INFO		20
-
-#define XMAC_HOST_INFO(NUM)		(0x00900UL + (NUM) * 0x8UL)
-
-#define XMAC_PA_DATA0			0x00b80UL
-#define XMAC_PA_DATA0_VAL		0x00000000ffffffffULL
-
-#define XMAC_PA_DATA1			0x00b88UL
-#define XMAC_PA_DATA1_VAL		0x00000000ffffffffULL
-
-#define XMAC_DEBUG_SEL			0x00b90UL
-#define  XMAC_DEBUG_SEL_XMAC		0x0000000000000078ULL
-#define  XMAC_DEBUG_SEL_MAC		0x0000000000000007ULL
-
-#define XMAC_TRAIN_VEC			0x00b98UL
-#define  XMAC_TRAIN_VEC_VAL		0x00000000ffffffffULL
-
-#define RXMAC_BT_CNT			0x00100UL
-#define  RXMAC_BT_CNT_COUNT		0x00000000ffffffffULL
-
-#define RXMAC_BC_FRM_CNT		0x00108UL
-#define  RXMAC_BC_FRM_CNT_COUNT		0x00000000001fffffULL
-
-#define RXMAC_MC_FRM_CNT		0x00110UL
-#define  RXMAC_MC_FRM_CNT_COUNT		0x00000000001fffffULL
-
-#define RXMAC_FRAG_CNT			0x00118UL
-#define  RXMAC_FRAG_CNT_COUNT		0x00000000001fffffULL
-
-#define RXMAC_HIST_CNT1			0x00120UL
-#define  RXMAC_HIST_CNT1_COUNT		0x00000000001fffffULL
-
-#define RXMAC_HIST_CNT2			0x00128UL
-#define  RXMAC_HIST_CNT2_COUNT		0x00000000001fffffULL
-
-#define RXMAC_HIST_CNT3			0x00130UL
-#define  RXMAC_HIST_CNT3_COUNT		0x00000000000fffffULL
-
-#define RXMAC_HIST_CNT4			0x00138UL
-#define  RXMAC_HIST_CNT4_COUNT		0x000000000007ffffULL
-
-#define RXMAC_HIST_CNT5			0x00140UL
-#define  RXMAC_HIST_CNT5_COUNT		0x000000000003ffffULL
-
-#define RXMAC_HIST_CNT6			0x00148UL
-#define  RXMAC_HIST_CNT6_COUNT		0x000000000000ffffULL
-
-#define RXMAC_MPSZER_CNT		0x00150UL
-#define  RXMAC_MPSZER_CNT_COUNT		0x00000000000000ffULL
-
-#define RXMAC_CRC_ER_CNT		0x00158UL
-#define  RXMAC_CRC_ER_CNT_COUNT		0x00000000000000ffULL
-
-#define RXMAC_CD_VIO_CNT		0x00160UL
-#define  RXMAC_CD_VIO_CNT_COUNT		0x00000000000000ffULL
-
-#define RXMAC_ALIGN_ERR_CNT		0x00168UL
-#define  RXMAC_ALIGN_ERR_CNT_COUNT	0x00000000000000ffULL
-
-#define TXMAC_FRM_CNT			0x00170UL
-#define  TXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL
-
-#define TXMAC_BYTE_CNT			0x00178UL
-#define  TXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL
-
-#define LINK_FAULT_CNT			0x00180UL
-#define  LINK_FAULT_CNT_COUNT		0x00000000000000ffULL
-
-#define RXMAC_HIST_CNT7			0x00188UL
-#define  RXMAC_HIST_CNT7_COUNT		0x0000000007ffffffULL
-
-#define XMAC_SM_REG			0x001a8UL
-#define  XMAC_SM_REG_STATE		0x00000000ffffffffULL
-
-#define XMAC_INTER1			0x001b0UL
-#define  XMAC_INTERN1_SIGNALS1		0x00000000ffffffffULL
-
-#define XMAC_INTER2			0x001b8UL
-#define  XMAC_INTERN2_SIGNALS2		0x00000000ffffffffULL
-
-/* BMAC registers, offset from np->mac_regs  */
-
-#define BTXMAC_SW_RST			0x00000UL
-#define  BTXMAC_SW_RST_RESET		0x0000000000000001ULL
-
-#define BRXMAC_SW_RST			0x00008UL
-#define  BRXMAC_SW_RST_RESET		0x0000000000000001ULL
-
-#define BMAC_SEND_PAUSE			0x00010UL
-#define  BMAC_SEND_PAUSE_SEND		0x0000000000010000ULL
-#define  BMAC_SEND_PAUSE_TIME		0x000000000000ffffULL
-
-#define BTXMAC_STATUS			0x00020UL
-#define  BTXMAC_STATUS_XMIT		0x0000000000000001ULL
-#define  BTXMAC_STATUS_UNDERRUN		0x0000000000000002ULL
-#define  BTXMAC_STATUS_MAX_PKT_ERR	0x0000000000000004ULL
-#define  BTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
-#define  BTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL
-
-#define BRXMAC_STATUS			0x00028UL
-#define  BRXMAC_STATUS_RX_PKT		0x0000000000000001ULL
-#define  BRXMAC_STATUS_OVERFLOW		0x0000000000000002ULL
-#define  BRXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000004ULL
-#define  BRXMAC_STATUS_ALIGN_ERR_EXP	0x0000000000000008ULL
-#define  BRXMAC_STATUS_CRC_ERR_EXP	0x0000000000000010ULL
-#define  BRXMAC_STATUS_LEN_ERR_EXP	0x0000000000000020ULL
-
-#define BMAC_CTRL_STATUS		0x00030UL
-#define  BMAC_CTRL_STATUS_PAUSE_RECV	0x0000000000000001ULL
-#define  BMAC_CTRL_STATUS_PAUSE		0x0000000000000002ULL
-#define  BMAC_CTRL_STATUS_NOPAUSE	0x0000000000000004ULL
-#define  BMAC_CTRL_STATUS_TIME		0x00000000ffff0000ULL
-#define  BMAC_CTRL_STATUS_TIME_SHIFT	16
-
-#define BTXMAC_STATUS_MASK		0x00040UL
-#define BRXMAC_STATUS_MASK		0x00048UL
-#define BMAC_CTRL_STATUS_MASK		0x00050UL
-
-#define BTXMAC_CONFIG			0x00060UL
-#define  BTXMAC_CONFIG_ENABLE		0x0000000000000001ULL
-#define  BTXMAC_CONFIG_FCS_DISABLE	0x0000000000000002ULL
-
-#define BRXMAC_CONFIG			0x00068UL
-#define  BRXMAC_CONFIG_DISCARD_DIS	0x0000000000000080ULL
-#define  BRXMAC_CONFIG_ADDR_FILT_EN	0x0000000000000040ULL
-#define  BRXMAC_CONFIG_HASH_FILT_EN	0x0000000000000020ULL
-#define  BRXMAC_CONFIG_PROMISC_GRP	0x0000000000000010ULL
-#define  BRXMAC_CONFIG_PROMISC		0x0000000000000008ULL
-#define  BRXMAC_CONFIG_STRIP_FCS	0x0000000000000004ULL
-#define  BRXMAC_CONFIG_STRIP_PAD	0x0000000000000002ULL
-#define  BRXMAC_CONFIG_ENABLE		0x0000000000000001ULL
-
-#define BMAC_CTRL_CONFIG		0x00070UL
-#define  BMAC_CTRL_CONFIG_TX_PAUSE_EN	0x0000000000000001ULL
-#define  BMAC_CTRL_CONFIG_RX_PAUSE_EN	0x0000000000000002ULL
-#define  BMAC_CTRL_CONFIG_PASS_CTRL	0x0000000000000004ULL
-
-#define BMAC_XIF_CONFIG			0x00078UL
-#define  BMAC_XIF_CONFIG_TX_OUTPUT_EN	0x0000000000000001ULL
-#define  BMAC_XIF_CONFIG_MII_LOOPBACK	0x0000000000000002ULL
-#define  BMAC_XIF_CONFIG_GMII_MODE	0x0000000000000008ULL
-#define  BMAC_XIF_CONFIG_LINK_LED	0x0000000000000020ULL
-#define  BMAC_XIF_CONFIG_LED_POLARITY	0x0000000000000040ULL
-#define  BMAC_XIF_CONFIG_25MHZ_CLOCK	0x0000000000000080ULL
-
-#define BMAC_MIN_FRAME			0x000a0UL
-#define  BMAC_MIN_FRAME_VAL		0x00000000000003ffULL
-
-#define BMAC_MAX_FRAME			0x000a8UL
-#define  BMAC_MAX_FRAME_MAX_BURST	0x000000003fff0000ULL
-#define  BMAC_MAX_FRAME_MAX_BURST_SHIFT	16
-#define  BMAC_MAX_FRAME_MAX_FRAME	0x0000000000003fffULL
-#define  BMAC_MAX_FRAME_MAX_FRAME_SHIFT	0
-
-#define BMAC_PREAMBLE_SIZE		0x000b0UL
-#define  BMAC_PREAMBLE_SIZE_VAL		0x00000000000003ffULL
-
-#define BMAC_CTRL_TYPE			0x000c8UL
-
-#define BMAC_ADDR0			0x00100UL
-#define  BMAC_ADDR0_ADDR0		0x000000000000ffffULL
-
-#define BMAC_ADDR1			0x00108UL
-#define  BMAC_ADDR1_ADDR1		0x000000000000ffffULL
-
-#define BMAC_ADDR2			0x00110UL
-#define  BMAC_ADDR2_ADDR2		0x000000000000ffffULL
-
-#define BMAC_NUM_ALT_ADDR		6
-
-#define BMAC_ALT_ADDR0(NUM)		(0x00118UL + (NUM)*0x18UL)
-#define  BMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL
-
-#define BMAC_ALT_ADDR1(NUM)		(0x00120UL + (NUM)*0x18UL)
-#define  BMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL
-
-#define BMAC_ALT_ADDR2(NUM)		(0x00128UL + (NUM)*0x18UL)
-#define  BMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL
-
-#define BMAC_FC_ADDR0			0x00268UL
-#define  BMAC_FC_ADDR0_ADDR0		0x000000000000ffffULL
-
-#define BMAC_FC_ADDR1			0x00270UL
-#define  BMAC_FC_ADDR1_ADDR1		0x000000000000ffffULL
-
-#define BMAC_FC_ADDR2			0x00278UL
-#define  BMAC_FC_ADDR2_ADDR2		0x000000000000ffffULL
-
-#define BMAC_ADD_FILT0			0x00298UL
-#define  BMAC_ADD_FILT0_FILT0		0x000000000000ffffULL
-
-#define BMAC_ADD_FILT1			0x002a0UL
-#define  BMAC_ADD_FILT1_FILT1		0x000000000000ffffULL
-
-#define BMAC_ADD_FILT2			0x002a8UL
-#define  BMAC_ADD_FILT2_FILT2		0x000000000000ffffULL
-
-#define BMAC_ADD_FILT12_MASK		0x002b0UL
-#define  BMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL
-
-#define BMAC_ADD_FILT00_MASK		0x002b8UL
-#define  BMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL
-
-#define BMAC_HASH_TBL(NUM)		(0x002c0UL + (NUM) * 0x8UL)
-#define BMAC_HASH_TBL_VAL		0x000000000000ffffULL
-
-#define BRXMAC_FRAME_CNT		0x00370
-#define  BRXMAC_FRAME_CNT_COUNT		0x000000000000ffffULL
-
-#define BRXMAC_MAX_LEN_ERR_CNT		0x00378
-
-#define BRXMAC_ALIGN_ERR_CNT		0x00380
-#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL
-
-#define BRXMAC_CRC_ERR_CNT		0x00388
-#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL
-
-#define BRXMAC_CODE_VIOL_ERR_CNT	0x00390
-#define  BRXMAC_CODE_VIOL_ERR_CNT_COUNT	0x000000000000ffffULL
-
-#define BMAC_STATE_MACHINE		0x003a0
-
-#define BMAC_ADDR_CMPEN			0x003f8UL
-#define  BMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
-#define  BMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
-#define  BMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
-#define  BMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
-#define  BMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
-#define  BMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
-#define  BMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
-#define  BMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
-#define  BMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
-#define  BMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
-#define  BMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
-#define  BMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
-#define  BMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
-#define  BMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
-#define  BMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
-#define  BMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL
-
-#define BMAC_NUM_HOST_INFO		9
-
-#define BMAC_HOST_INFO(NUM)		(0x00400UL + (NUM) * 0x8UL)
-
-#define BTXMAC_BYTE_CNT			0x00448UL
-#define  BTXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL
-
-#define BTXMAC_FRM_CNT			0x00450UL
-#define  BTXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL
-
-#define BRXMAC_BYTE_CNT			0x00458UL
-#define  BRXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL
-
-#define HOST_INFO_MPR			0x0000000000000100ULL
-#define HOST_INFO_MACRDCTBLN		0x0000000000000007ULL
-
-/* XPCS registers, offset from np->regs + np->xpcs_off  */
-
-#define XPCS_CONTROL1			(FZC_MAC + 0x00000UL)
-#define  XPCS_CONTROL1_RESET		0x0000000000008000ULL
-#define  XPCS_CONTROL1_LOOPBACK		0x0000000000004000ULL
-#define  XPCS_CONTROL1_SPEED_SELECT3	0x0000000000002000ULL
-#define  XPCS_CONTROL1_CSR_LOW_PWR	0x0000000000000800ULL
-#define  XPCS_CONTROL1_CSR_SPEED1	0x0000000000000040ULL
-#define  XPCS_CONTROL1_CSR_SPEED0	0x000000000000003cULL
-
-#define XPCS_STATUS1			(FZC_MAC + 0x00008UL)
-#define  XPCS_STATUS1_CSR_FAULT		0x0000000000000080ULL
-#define  XPCS_STATUS1_CSR_RXLNK_STAT	0x0000000000000004ULL
-#define  XPCS_STATUS1_CSR_LPWR_ABLE	0x0000000000000002ULL
-
-#define XPCS_DEVICE_IDENTIFIER		(FZC_MAC + 0x00010UL)
-#define  XPCS_DEVICE_IDENTIFIER_VAL	0x00000000ffffffffULL
-
-#define XPCS_SPEED_ABILITY		(FZC_MAC + 0x00018UL)
-#define  XPCS_SPEED_ABILITY_10GIG	0x0000000000000001ULL
-
-#define XPCS_DEV_IN_PKG			(FZC_MAC + 0x00020UL)
-#define  XPCS_DEV_IN_PKG_CSR_VEND2	0x0000000080000000ULL
-#define  XPCS_DEV_IN_PKG_CSR_VEND1	0x0000000040000000ULL
-#define  XPCS_DEV_IN_PKG_DTE_XS		0x0000000000000020ULL
-#define  XPCS_DEV_IN_PKG_PHY_XS		0x0000000000000010ULL
-#define  XPCS_DEV_IN_PKG_PCS		0x0000000000000008ULL
-#define  XPCS_DEV_IN_PKG_WIS		0x0000000000000004ULL
-#define  XPCS_DEV_IN_PKG_PMD_PMA	0x0000000000000002ULL
-#define  XPCS_DEV_IN_PKG_CLS22		0x0000000000000001ULL
-
-#define XPCS_CONTROL2			(FZC_MAC + 0x00028UL)
-#define  XPCS_CONTROL2_CSR_PSC_SEL	0x0000000000000003ULL
-
-#define XPCS_STATUS2			(FZC_MAC + 0x00030UL)
-#define  XPCS_STATUS2_CSR_DEV_PRES	0x000000000000c000ULL
-#define  XPCS_STATUS2_CSR_TX_FAULT	0x0000000000000800ULL
-#define  XPCS_STATUS2_CSR_RCV_FAULT	0x0000000000000400ULL
-#define  XPCS_STATUS2_TEN_GBASE_W	0x0000000000000004ULL
-#define  XPCS_STATUS2_TEN_GBASE_X	0x0000000000000002ULL
-#define  XPCS_STATUS2_TEN_GBASE_R	0x0000000000000001ULL
-
-#define XPCS_PKG_ID			(FZC_MAC + 0x00038UL)
-#define  XPCS_PKG_ID_VAL		0x00000000ffffffffULL
-
-#define XPCS_STATUS(IDX)		(FZC_MAC + 0x00040UL)
-#define  XPCS_STATUS_CSR_LANE_ALIGN	0x0000000000001000ULL
-#define  XPCS_STATUS_CSR_PATTEST_CAP	0x0000000000000800ULL
-#define  XPCS_STATUS_CSR_LANE3_SYNC	0x0000000000000008ULL
-#define  XPCS_STATUS_CSR_LANE2_SYNC	0x0000000000000004ULL
-#define  XPCS_STATUS_CSR_LANE1_SYNC	0x0000000000000002ULL
-#define  XPCS_STATUS_CSR_LANE0_SYNC	0x0000000000000001ULL
-
-#define XPCS_TEST_CONTROL		(FZC_MAC + 0x00048UL)
-#define  XPCS_TEST_CONTROL_TXTST_EN	0x0000000000000004ULL
-#define  XPCS_TEST_CONTROL_TPAT_SEL	0x0000000000000003ULL
-
-#define XPCS_CFG_VENDOR1		(FZC_MAC + 0x00050UL)
-#define  XPCS_CFG_VENDOR1_DBG_IOTST	0x0000000000000080ULL
-#define  XPCS_CFG_VENDOR1_DBG_SEL	0x0000000000000078ULL
-#define  XPCS_CFG_VENDOR1_BYPASS_DET	0x0000000000000004ULL
-#define  XPCS_CFG_VENDOR1_TXBUF_EN	0x0000000000000002ULL
-#define  XPCS_CFG_VENDOR1_XPCS_EN	0x0000000000000001ULL
-
-#define XPCS_DIAG_VENDOR2		(FZC_MAC + 0x00058UL)
-#define  XPCS_DIAG_VENDOR2_SSM_LANE3	0x0000000001e00000ULL
-#define  XPCS_DIAG_VENDOR2_SSM_LANE2	0x00000000001e0000ULL
-#define  XPCS_DIAG_VENDOR2_SSM_LANE1	0x000000000001e000ULL
-#define  XPCS_DIAG_VENDOR2_SSM_LANE0	0x0000000000001e00ULL
-#define  XPCS_DIAG_VENDOR2_EBUF_SM	0x00000000000001feULL
-#define  XPCS_DIAG_VENDOR2_RCV_SM	0x0000000000000001ULL
-
-#define XPCS_MASK1			(FZC_MAC + 0x00060UL)
-#define  XPCS_MASK1_FAULT_MASK		0x0000000000000080ULL
-#define  XPCS_MASK1_RXALIGN_STAT_MSK	0x0000000000000004ULL
-
-#define XPCS_PKT_COUNT			(FZC_MAC + 0x00068UL)
-#define  XPCS_PKT_COUNT_TX		0x00000000ffff0000ULL
-#define  XPCS_PKT_COUNT_RX		0x000000000000ffffULL
-
-#define XPCS_TX_SM			(FZC_MAC + 0x00070UL)
-#define  XPCS_TX_SM_VAL			0x000000000000000fULL
-
-#define XPCS_DESKEW_ERR_CNT		(FZC_MAC + 0x00078UL)
-#define  XPCS_DESKEW_ERR_CNT_VAL	0x00000000000000ffULL
-
-#define XPCS_SYMERR_CNT01		(FZC_MAC + 0x00080UL)
-#define  XPCS_SYMERR_CNT01_LANE1	0x00000000ffff0000ULL
-#define  XPCS_SYMERR_CNT01_LANE0	0x000000000000ffffULL
-
-#define XPCS_SYMERR_CNT23		(FZC_MAC + 0x00088UL)
-#define  XPCS_SYMERR_CNT23_LANE3	0x00000000ffff0000ULL
-#define  XPCS_SYMERR_CNT23_LANE2	0x000000000000ffffULL
-
-#define XPCS_TRAINING_VECTOR		(FZC_MAC + 0x00090UL)
-#define  XPCS_TRAINING_VECTOR_VAL	0x00000000ffffffffULL
-
-/* PCS registers, offset from np->regs + np->pcs_off  */
-
-#define PCS_MII_CTL			(FZC_MAC + 0x00000UL)
-#define  PCS_MII_CTL_RST		0x0000000000008000ULL
-#define  PCS_MII_CTL_10_100_SPEED	0x0000000000002000ULL
-#define  PCS_MII_AUTONEG_EN		0x0000000000001000ULL
-#define  PCS_MII_PWR_DOWN		0x0000000000000800ULL
-#define  PCS_MII_ISOLATE		0x0000000000000400ULL
-#define  PCS_MII_AUTONEG_RESTART	0x0000000000000200ULL
-#define  PCS_MII_DUPLEX			0x0000000000000100ULL
-#define  PCS_MII_COLL_TEST		0x0000000000000080ULL
-#define  PCS_MII_1000MB_SPEED		0x0000000000000040ULL
-
-#define PCS_MII_STAT			(FZC_MAC + 0x00008UL)
-#define  PCS_MII_STAT_EXT_STATUS	0x0000000000000100ULL
-#define  PCS_MII_STAT_AUTONEG_DONE	0x0000000000000020ULL
-#define  PCS_MII_STAT_REMOTE_FAULT	0x0000000000000010ULL
-#define  PCS_MII_STAT_AUTONEG_ABLE	0x0000000000000008ULL
-#define  PCS_MII_STAT_LINK_STATUS	0x0000000000000004ULL
-#define  PCS_MII_STAT_JABBER_DET	0x0000000000000002ULL
-#define  PCS_MII_STAT_EXT_CAP		0x0000000000000001ULL
-
-#define PCS_MII_ADV			(FZC_MAC + 0x00010UL)
-#define  PCS_MII_ADV_NEXT_PAGE		0x0000000000008000ULL
-#define  PCS_MII_ADV_ACK		0x0000000000004000ULL
-#define  PCS_MII_ADV_REMOTE_FAULT	0x0000000000003000ULL
-#define  PCS_MII_ADV_ASM_DIR		0x0000000000000100ULL
-#define  PCS_MII_ADV_PAUSE		0x0000000000000080ULL
-#define  PCS_MII_ADV_HALF_DUPLEX	0x0000000000000040ULL
-#define  PCS_MII_ADV_FULL_DUPLEX	0x0000000000000020ULL
-
-#define PCS_MII_PARTNER			(FZC_MAC + 0x00018UL)
-#define  PCS_MII_PARTNER_NEXT_PAGE	0x0000000000008000ULL
-#define  PCS_MII_PARTNER_ACK		0x0000000000004000ULL
-#define  PCS_MII_PARTNER_REMOTE_FAULT	0x0000000000002000ULL
-#define  PCS_MII_PARTNER_PAUSE		0x0000000000000180ULL
-#define  PCS_MII_PARTNER_HALF_DUPLEX	0x0000000000000040ULL
-#define  PCS_MII_PARTNER_FULL_DUPLEX	0x0000000000000020ULL
-
-#define PCS_CONF			(FZC_MAC + 0x00020UL)
-#define  PCS_CONF_MASK			0x0000000000000040ULL
-#define  PCS_CONF_10MS_TMR_OVERRIDE	0x0000000000000020ULL
-#define  PCS_CONF_JITTER_STUDY		0x0000000000000018ULL
-#define  PCS_CONF_SIGDET_ACTIVE_LOW	0x0000000000000004ULL
-#define  PCS_CONF_SIGDET_OVERRIDE	0x0000000000000002ULL
-#define  PCS_CONF_ENABLE		0x0000000000000001ULL
-
-#define PCS_STATE			(FZC_MAC + 0x00028UL)
-#define  PCS_STATE_D_PARTNER_FAIL	0x0000000020000000ULL
-#define  PCS_STATE_D_WAIT_C_CODES_ACK	0x0000000010000000ULL
-#define  PCS_STATE_D_SYNC_LOSS		0x0000000008000000ULL
-#define  PCS_STATE_D_NO_GOOD_C_CODES	0x0000000004000000ULL
-#define  PCS_STATE_D_SERDES		0x0000000002000000ULL
-#define  PCS_STATE_D_BREAKLINK_C_CODES	0x0000000001000000ULL
-#define  PCS_STATE_L_SIGDET		0x0000000000400000ULL
-#define  PCS_STATE_L_SYNC_LOSS		0x0000000000200000ULL
-#define  PCS_STATE_L_C_CODES		0x0000000000100000ULL
-#define  PCS_STATE_LINK_CFG_STATE	0x000000000001e000ULL
-#define  PCS_STATE_SEQ_DET_STATE	0x0000000000001800ULL
-#define  PCS_STATE_WORD_SYNC_STATE	0x0000000000000700ULL
-#define  PCS_STATE_NO_IDLE		0x000000000000000fULL
-
-#define PCS_INTERRUPT			(FZC_MAC + 0x00030UL)
-#define  PCS_INTERRUPT_LSTATUS		0x0000000000000004ULL
-
-#define PCS_DPATH_MODE			(FZC_MAC + 0x000a0UL)
-#define  PCS_DPATH_MODE_PCS		0x0000000000000000ULL
-#define  PCS_DPATH_MODE_MII		0x0000000000000002ULL
-#define  PCS_DPATH_MODE_LINKUP_F_ENAB	0x0000000000000001ULL
-
-#define PCS_PKT_CNT			(FZC_MAC + 0x000c0UL)
-#define  PCS_PKT_CNT_RX			0x0000000007ff0000ULL
-#define  PCS_PKT_CNT_TX			0x00000000000007ffULL
-
-#define MIF_BB_MDC			(FZC_MAC + 0x16000UL)
-#define  MIF_BB_MDC_CLK			0x0000000000000001ULL
-
-#define MIF_BB_MDO			(FZC_MAC + 0x16008UL)
-#define  MIF_BB_MDO_DAT			0x0000000000000001ULL
-
-#define MIF_BB_MDO_EN			(FZC_MAC + 0x16010UL)
-#define  MIF_BB_MDO_EN_VAL		0x0000000000000001ULL
-
-#define MIF_FRAME_OUTPUT		(FZC_MAC + 0x16018UL)
-#define  MIF_FRAME_OUTPUT_ST		0x00000000c0000000ULL
-#define  MIF_FRAME_OUTPUT_ST_SHIFT	30
-#define  MIF_FRAME_OUTPUT_OP_ADDR	0x0000000000000000ULL
-#define  MIF_FRAME_OUTPUT_OP_WRITE	0x0000000010000000ULL
-#define  MIF_FRAME_OUTPUT_OP_READ_INC	0x0000000020000000ULL
-#define  MIF_FRAME_OUTPUT_OP_READ	0x0000000030000000ULL
-#define  MIF_FRAME_OUTPUT_OP_SHIFT	28
-#define  MIF_FRAME_OUTPUT_PORT		0x000000000f800000ULL
-#define  MIF_FRAME_OUTPUT_PORT_SHIFT	23
-#define  MIF_FRAME_OUTPUT_REG		0x00000000007c0000ULL
-#define  MIF_FRAME_OUTPUT_REG_SHIFT	18
-#define  MIF_FRAME_OUTPUT_TA		0x0000000000030000ULL
-#define  MIF_FRAME_OUTPUT_TA_SHIFT	16
-#define  MIF_FRAME_OUTPUT_DATA		0x000000000000ffffULL
-#define  MIF_FRAME_OUTPUT_DATA_SHIFT	0
-
-#define MDIO_ADDR_OP(port, dev, reg) \
-	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
-	 MIF_FRAME_OUTPUT_OP_ADDR | \
-	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
-	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
-	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
-	 (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))
-
-#define MDIO_READ_OP(port, dev) \
-	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
-	 MIF_FRAME_OUTPUT_OP_READ | \
-	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
-	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
-	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
-
-#define MDIO_WRITE_OP(port, dev, data) \
-	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
-	 MIF_FRAME_OUTPUT_OP_WRITE | \
-	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
-	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
-	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
-	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
-
-#define MII_READ_OP(port, reg) \
-	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
-	 (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
-	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
-	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
-	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
-
-#define MII_WRITE_OP(port, reg, data) \
-	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
-	 (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
-	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
-	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
-	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
-	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
-
-#define MIF_CONFIG			(FZC_MAC + 0x16020UL)
-#define  MIF_CONFIG_ATCA_GE		0x0000000000010000ULL
-#define  MIF_CONFIG_INDIRECT_MODE	0x0000000000008000ULL
-#define  MIF_CONFIG_POLL_PRT_PHYADDR	0x0000000000003c00ULL
-#define  MIF_CONFIG_POLL_DEV_REG_ADDR	0x00000000000003e0ULL
-#define  MIF_CONFIG_BB_MODE		0x0000000000000010ULL
-#define  MIF_CONFIG_POLL_EN		0x0000000000000008ULL
-#define  MIF_CONFIG_BB_SER_SEL		0x0000000000000006ULL
-#define  MIF_CONFIG_MANUAL_MODE		0x0000000000000001ULL
-
-#define MIF_POLL_STATUS			(FZC_MAC + 0x16028UL)
-#define  MIF_POLL_STATUS_DATA		0x00000000ffff0000ULL
-#define  MIF_POLL_STATUS_STAT		0x000000000000ffffULL
-
-#define MIF_POLL_MASK			(FZC_MAC + 0x16030UL)
-#define  MIF_POLL_MASK_VAL		0x000000000000ffffULL
-
-#define MIF_SM				(FZC_MAC + 0x16038UL)
-#define  MIF_SM_PORT_ADDR		0x00000000001f0000ULL
-#define  MIF_SM_MDI_1			0x0000000000004000ULL
-#define  MIF_SM_MDI_0			0x0000000000002400ULL
-#define  MIF_SM_MDCLK			0x0000000000001000ULL
-#define  MIF_SM_MDO_EN			0x0000000000000800ULL
-#define  MIF_SM_MDO			0x0000000000000400ULL
-#define  MIF_SM_MDI			0x0000000000000200ULL
-#define  MIF_SM_CTL			0x00000000000001c0ULL
-#define  MIF_SM_EX			0x000000000000003fULL
-
-#define MIF_STATUS			(FZC_MAC + 0x16040UL)
-#define  MIF_STATUS_MDINT1		0x0000000000000020ULL
-#define  MIF_STATUS_MDINT0		0x0000000000000010ULL
-
-#define MIF_MASK			(FZC_MAC + 0x16048UL)
-#define  MIF_MASK_MDINT1		0x0000000000000020ULL
-#define  MIF_MASK_MDINT0		0x0000000000000010ULL
-#define  MIF_MASK_PEU_ERR		0x0000000000000008ULL
-#define  MIF_MASK_YC			0x0000000000000004ULL
-#define  MIF_MASK_XGE_ERR0		0x0000000000000002ULL
-#define  MIF_MASK_MIF_INIT_DONE		0x0000000000000001ULL
-
-#define ENET_SERDES_RESET		(FZC_MAC + 0x14000UL)
-#define  ENET_SERDES_RESET_1		0x0000000000000002ULL
-#define  ENET_SERDES_RESET_0		0x0000000000000001ULL
-
-#define ENET_SERDES_CFG			(FZC_MAC + 0x14008UL)
-#define  ENET_SERDES_BE_LOOPBACK	0x0000000000000002ULL
-#define  ENET_SERDES_CFG_FORCE_RDY	0x0000000000000001ULL
-
-#define ENET_SERDES_0_PLL_CFG		(FZC_MAC + 0x14010UL)
-#define  ENET_SERDES_PLL_FBDIV0		0x0000000000000001ULL
-#define  ENET_SERDES_PLL_FBDIV1		0x0000000000000002ULL
-#define  ENET_SERDES_PLL_FBDIV2		0x0000000000000004ULL
-#define  ENET_SERDES_PLL_HRATE0		0x0000000000000008ULL
-#define  ENET_SERDES_PLL_HRATE1		0x0000000000000010ULL
-#define  ENET_SERDES_PLL_HRATE2		0x0000000000000020ULL
-#define  ENET_SERDES_PLL_HRATE3		0x0000000000000040ULL
-
-#define ENET_SERDES_0_CTRL_CFG		(FZC_MAC + 0x14018UL)
-#define  ENET_SERDES_CTRL_SDET_0	0x0000000000000001ULL
-#define  ENET_SERDES_CTRL_SDET_1	0x0000000000000002ULL
-#define  ENET_SERDES_CTRL_SDET_2	0x0000000000000004ULL
-#define  ENET_SERDES_CTRL_SDET_3	0x0000000000000008ULL
-#define  ENET_SERDES_CTRL_EMPH_0	0x0000000000000070ULL
-#define  ENET_SERDES_CTRL_EMPH_0_SHIFT	4
-#define  ENET_SERDES_CTRL_EMPH_1	0x0000000000000380ULL
-#define  ENET_SERDES_CTRL_EMPH_1_SHIFT	7
-#define  ENET_SERDES_CTRL_EMPH_2	0x0000000000001c00ULL
-#define  ENET_SERDES_CTRL_EMPH_2_SHIFT	10
-#define  ENET_SERDES_CTRL_EMPH_3	0x000000000000e000ULL
-#define  ENET_SERDES_CTRL_EMPH_3_SHIFT	13
-#define  ENET_SERDES_CTRL_LADJ_0	0x0000000000070000ULL
-#define  ENET_SERDES_CTRL_LADJ_0_SHIFT	16
-#define  ENET_SERDES_CTRL_LADJ_1	0x0000000000380000ULL
-#define  ENET_SERDES_CTRL_LADJ_1_SHIFT	19
-#define  ENET_SERDES_CTRL_LADJ_2	0x0000000001c00000ULL
-#define  ENET_SERDES_CTRL_LADJ_2_SHIFT	22
-#define  ENET_SERDES_CTRL_LADJ_3	0x000000000e000000ULL
-#define  ENET_SERDES_CTRL_LADJ_3_SHIFT	25
-#define  ENET_SERDES_CTRL_RXITERM_0	0x0000000010000000ULL
-#define  ENET_SERDES_CTRL_RXITERM_1	0x0000000020000000ULL
-#define  ENET_SERDES_CTRL_RXITERM_2	0x0000000040000000ULL
-#define  ENET_SERDES_CTRL_RXITERM_3	0x0000000080000000ULL
-
-#define ENET_SERDES_0_TEST_CFG		(FZC_MAC + 0x14020UL)
-#define  ENET_SERDES_TEST_MD_0		0x0000000000000003ULL
-#define  ENET_SERDES_TEST_MD_0_SHIFT	0
-#define  ENET_SERDES_TEST_MD_1		0x000000000000000cULL
-#define  ENET_SERDES_TEST_MD_1_SHIFT	2
-#define  ENET_SERDES_TEST_MD_2		0x0000000000000030ULL
-#define  ENET_SERDES_TEST_MD_2_SHIFT	4
-#define  ENET_SERDES_TEST_MD_3		0x00000000000000c0ULL
-#define  ENET_SERDES_TEST_MD_3_SHIFT	6
-
-#define ENET_TEST_MD_NO_LOOPBACK	0x0
-#define ENET_TEST_MD_EWRAP		0x1
-#define ENET_TEST_MD_PAD_LOOPBACK	0x2
-#define ENET_TEST_MD_REV_LOOPBACK	0x3
-
-#define ENET_SERDES_1_PLL_CFG		(FZC_MAC + 0x14028UL)
-#define ENET_SERDES_1_CTRL_CFG		(FZC_MAC + 0x14030UL)