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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-12 23:04:46 -0700
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-11 02:33:43 -0700
commite689cf4a042772f727450035b102579b0c01bdc7 (patch)
treef2b17aa21b8358a8f7589fed46fa08688b439464 /drivers/net/cassini.h
parent8efc91254fda97ee78e2e0b8e016120e664131de (diff)
cassini/niu/sun*: Move the Sun drivers
Moves the Sun drivers into drivers/net/ethernet/sun/ and make the necessary Kconfig and Makefile changes. Oliver Hartkopp <socketcan@hartkopp.net> suggested removing the sun* prefix on the driver names. This type of change I will leave up to the driver maintainers. CC: Sam Creasey <sammy@sammy.net> CC: Adrian Sun <asun@darksunrising.com> CC: Benjamin Herrenscmidt <benh@kernel.crashing.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/cassini.h')
-rw-r--r--drivers/net/cassini.h2914
1 files changed, 0 insertions, 2914 deletions
diff --git a/drivers/net/cassini.h b/drivers/net/cassini.h
deleted file mode 100644
index b361424d5f5..00000000000
--- a/drivers/net/cassini.h
+++ /dev/null
@@ -1,2914 +0,0 @@
-/* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
- * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
- *
- * Copyright (C) 2004 Sun Microsystems Inc.
- * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * vendor id: 0x108E (Sun Microsystems, Inc.)
- * device id: 0xabba (Cassini)
- * revision ids: 0x01 = Cassini
- * 0x02 = Cassini rev 2
- * 0x10 = Cassini+
- * 0x11 = Cassini+ 0.2u
- *
- * vendor id: 0x100b (National Semiconductor)
- * device id: 0x0035 (DP83065/Saturn)
- * revision ids: 0x30 = Saturn B2
- *
- * rings are all offset from 0.
- *
- * there are two clock domains:
- * PCI: 33/66MHz clock
- * chip: 125MHz clock
- */
-
-#ifndef _CASSINI_H
-#define _CASSINI_H
-
-/* cassini register map: 2M memory mapped in 32-bit memory space accessible as
- * 32-bit words. there is no i/o port access. REG_ addresses are
- * shared between cassini and cassini+. REG_PLUS_ addresses only
- * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
- */
-#define CAS_ID_REV2 0x02
-#define CAS_ID_REVPLUS 0x10
-#define CAS_ID_REVPLUS02u 0x11
-#define CAS_ID_REVSATURNB2 0x30
-
-/** global resources **/
-
-/* this register sets the weights for the weighted round robin arbiter. e.g.,
- * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
- * for its next turn to access the pci bus.
- * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
- * DEFAULT: 0x0, SIZE: 5 bits
- */
-#define REG_CAWR 0x0004 /* core arbitration weight */
-#define CAWR_RX_DMA_WEIGHT_SHIFT 0
-#define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */
-#define CAWR_TX_DMA_WEIGHT_SHIFT 2
-#define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */
-#define CAWR_RR_DIS 0x10 /* [4] */
-
-/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
- * sizes determined by length of packet or descriptor transfer and the
- * max length allowed by the target.
- * DEFAULT: 0x0, SIZE: 1 bit
- */
-#define REG_INF_BURST 0x0008 /* infinite burst enable reg */
-#define INF_BURST_EN 0x1 /* enable */
-
-/* top level interrupts [0-9] are auto-cleared to 0 when the status
- * register is read. second level interrupts [13 - 18] are cleared at
- * the source. tx completion register 3 is replicated in [19 - 31]
- * DEFAULT: 0x00000000, SIZE: 29 bits
- */
-#define REG_INTR_STATUS 0x000C /* interrupt status register */
-#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
- xferred from host queue to
- TX FIFO */
-#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
- TX FIFO. i.e.,
- TX Kick == TX complete. if
- PACED_MODE set, then TX FIFO
- also empty */
-#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
- FIFO */
-#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
- corrupted. FATAL ERROR */
-#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
- from RX FIFO to host mem.
- RX completion reg updated.
- may be delayed by recv
- intr blanking. */
-#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
- RX Kick == RX complete */
-#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
- corrupted. FATAL ERROR */
-#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
- ring to post descriptors.
- RX complete head incr to
- almost reach RX complete
- tail */
-#define INTR_RX_BUF_AE 0x00000100 /* less than the
- programmable threshold #
- of free descr avail for
- hw use */
-#define INTR_RX_COMP_AF 0x00000200 /* less than the
- programmable threshold #
- of descr spaces for hw
- use in completion descr
- ring */
-#define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC !=
- len of non-reassembly pkt
- from fifo during DMA or
- header parser provides TCP
- header and payload size >
- MAC packet size.
- FATAL ERROR */
-#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
- bit will be set if an interrupt
- generated on the pci bus. useful
- when driver is polling for
- interrupts */
-#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
-#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
- least 1 unmasked interrupt set */
-#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
- least 1 unmasked interrupt set */
-#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
- at least 1 unmasked interrupt
- set */
-#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
- 1 unmasked interrupt set */
-#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
- BIF has at least 1 unmasked
- interrupt set */
-#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
- 3 reg data */
-#define INTR_TX_COMP_3_SHIFT 19
-#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
- INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
- INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
- INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
- INTR_MAC_CTRL_STATUS)
-
-/* determines which status events will cause an interrupt. layout same
- * as REG_INTR_STATUS.
- * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
- */
-#define REG_INTR_MASK 0x0010 /* Interrupt mask */
-
-/* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
- * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
- * DEFAULT: 0x00000000, SIZE: 12 bits
- */
-#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
- (used w/ status alias) */
-/* same as REG_INTR_STATUS except that only bits cleared are those selected by
- * REG_ALIAS_CLEAR
- * DEFAULT: 0x00000000, SIZE: 29 bits
- */
-#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
- (selective clear) */
-
-/* DEFAULT: 0x0, SIZE: 3 bits */
-#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
-#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
- set if no ACK64# during ABS64 cycle
- in Cassini. */
-#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
- no read retry after 2^15 clocks */
-#define PCI_ERR_OTHER 0x04 /* other PCI errors */
-#define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req.
- unused in Cassini. */
-#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
- unused in Cassini. */
-#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
- DMA. unused in cassini. */
-
-/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
- * causes an interrupt to be generated.
- * DEFAULT: 0x7, SIZE: 3 bits
- */
-#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
-
-/* used to configure PCI related parameters that are not in PCI config space.
- * DEFAULT: 0bxx000, SIZE: 5 bits
- */
-#define REG_BIM_CFG 0x1008 /* BIM Configuration */
-#define BIM_CFG_RESERVED0 0x001 /* reserved */
-#define BIM_CFG_RESERVED1 0x002 /* reserved */
-#define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
-#define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
-#define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
-#define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */
-#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
-#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
-#define BIM_CFG_RESERVED2 0x100 /* reserved */
-#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
- reset. reserved in Cassini. */
-#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
- reserved in Cassini. */
-#define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0.
- reserved in Cassini. */
-
-/* DEFAULT: 0x00000000, SIZE: 32 bits */
-#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
-#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
- machine bits [21:0] */
-#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
- machine bits [6:0] */
-
-/* writing to SW_RESET_TX and SW_RESET_RX will issue a global
- * reset. poll until TX and RX read back as 0's for completion.
- */
-#define REG_SW_RESET 0x1010 /* Software reset */
-#define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until
- cleared to 0. */
-#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
- cleared to 0. */
-#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
- resets PHY and anything else
- connected to RSTOUT#. RSTOUT#
- is also activated by local PCI
- reset when hot-swap is being
- done. */
-#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
- this bit set, PCS and SLINK
- modules won't be reset.
- i.e., link won't drop. */
-#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
-#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
- 0b000: ARB_IDLE1
- 0b001: ARB_IDLE2
- 0b010: ARB_WB_ACK
- 0b011: ARB_WB_WAT
- 0b100: ARB_RB_ACK
- 0b101: ARB_RB_WAT
- 0b110: ARB_RB_END
- 0b111: ARB_WB_END */
-#define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
- 0b00: RD_PCI_WAT
- 0b01: RD_PCI_RDY
- 0b11: RD_PCI_ACK */
-#define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
- 0b00: AD_IDL_RX
- 0b01: AD_ACK_RX
- 0b10: AD_ACK_TX
- 0b11: AD_IDL_TX */
-#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
- 0b00: WR_PCI_WAT
- 0b01: WR_PCI_RDY
- 0b11: WR_PCI_ACK */
-#define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits:
- 0b000: ARB_IDLE1
- 0b001: ARB_IDLE2
- 0b010: ARB_TX_ACK
- 0b011: ARB_TX_WAT
- 0b100: ARB_RX_ACK
- 0b110: ARB_RX_WAT */
-
-/* Cassini only. 64-bit register used to check PCI datapath. when read,
- * value written has both lower and upper 32-bit halves rotated to the right
- * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
- */
-#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
- Cassini+: reserved */
-
-/* output enables are provided for each device's chip select and for the rest
- * of the outputs from cassini to its local bus devices. two sw programmable
- * bits are connected to general purpus control/status bits.
- * DEFAULT: 0x7
- */
-#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
- output EN. default: 0x7 */
-#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
- OE signal output enable on the
- local bus interface. these
- are shared between both local
- bus devices. tristate when 0. */
-#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
-#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
- select output enable */
-#define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */
-#define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */
-#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
-
-/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
- * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
- * _DATA_HI should be the last access of the sequence.
- * DEFAULT: undefined
- */
-#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
- purposes. */
-#define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
-#define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1
- read buffer access = 0 */
-/* DEFAULT: undefined */
-#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
-#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
-
-/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
- * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
- */
-#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
- control/status */
-#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
-#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
- Cassini only. reserved in
- Cassini+. */
-#define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
- buffer. */
-#define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write
- buffer. Cassini only. reserved
- in Cassini+. */
-#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
-#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
-#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
- Cassini only. reserved in
- Cassini+. */
-#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
- Cassini only. reserved in
- Cassini+. */
-
-/* ASUN: i'm not sure what this does as it's not in the spec.
- * DEFAULT: 0xFC
- */
-#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
- select register */
-
-/* enable probe monitoring mode and select data appearing on the P_A* bus. bit
- * values for _SEL_HI_MASK and _SEL_LOW_MASK:
- * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
- * wtc empty r, post pci)
- * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
- * pci rpkt comp, txdma wr req, txdma wr ack,
- * txdma wr rdy, txdma wr xfr done)
- * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
- * rd arb state, rd pci state)
- * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
- * wrpci state)
- * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
- * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
- * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
- * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
- * the following are not available in Cassini:
- * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
- * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
- */
-#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
-#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
- driven on local bus P_A[15:0]
- for debugging */
-#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
- 0x03 = mac[1:0]
- 0x0C = rx[1:0]
- 0x30 = tx[1:0]
- 0xC0 = hp[1:0] */
-#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
- on P_A[15:8]. see above for
- values. */
-#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
- on P_A[7:0]. see above for
- values. */
-
-/* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
- DEFAULT: 0x1F */
-#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
- register 2 for INTB */
-#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
-/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
- * all of the alternate (2-4) INTR registers while _1 corresponds to only
- * _MASK_1 and _STATUS_1 registers.
- * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
- */
-#define INTR_RX_DONE_ALT 0x01
-#define INTR_RX_COMP_FULL_ALT 0x02
-#define INTR_RX_COMP_AF_ALT 0x04
-#define INTR_RX_BUF_UNAVAIL_1 0x08
-#define INTR_RX_BUF_AE_1 0x10 /* almost empty */
-#define INTRN_MASK_RX_EN 0x80
-#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
- INTR_RX_COMP_FULL_ALT | \
- INTR_RX_COMP_AF_ALT | \
- INTR_RX_BUF_UNAVAIL_1 | \
- INTR_RX_BUF_AE_1)
-#define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status
- register 2 for INTB. default: 0x1F */
-#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
-#define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the
- flags are set. enables desc ring. */
-
-#define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
- register 2 for INTB */
-#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
-
-#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
- register alias 2 for INTB */
-#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
-
-#define REG_SATURN_PCFG 0x106c /* pin configuration register for
- integrated macphy */
-
-#define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */
-#define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */
-#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
-#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
-#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
-#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
- 0 = normal */
-#define SATURN_PCFG_MTP 0x00000080 /* test point select */
-#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
- GMII on SERDES pins for
- monitoring. */
-#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
- pins configed as outputs.
- for power saving when using
- internal phy. */
-#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
- polarity from strapping
- value.
- 1 = mac core led ctrl
- polarity active low. */
-
-
-/** transmit dma registers **/
-#define MAX_TX_RINGS_SHIFT 2
-#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
-#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
-
-/* TX configuration.
- * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
- * DEFAULT: 0x3F000001
- */
-#define REG_TX_CFG 0x2004 /* TX config */
-#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
- will stop after xfer of current
- buffer has been completed. */
-#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
- accessed w/ FIFO addr
- and data registers.
- TX DMA should be
- disabled. */
-#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
- ring 1. */
-#define TX_CFG_DESC_RING0_SHIFT 2
-#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
-#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
-#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
- TX FIFO becomes empty.
- if 0, TX_ALL set
- if descr queue empty. */
-#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
-#define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at
- the end of every packet kicked
- through Q1. */
-#define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at
- the end of every packet kicked
- through Q2. */
-#define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at
- the end of every packet kicked
- through Q3 */
-#define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at
- the end of every packet kicked
- through Q4 */
-#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
- writeback */
-#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
- connection
- 0b00: tx mac req,
- tx mac retry req,
- tx ack and tx tag.
- 0b01: txdma rd req,
- txdma rd ack,
- txdma rd rdy,
- txdma rd type0
- 0b11: txdma wr req,
- txdma wr ack,
- txdma wr rdy,
- txdma wr xfr done. */
-#define TX_CFG_CTX_SEL_SHIFT 30
-
-/* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
- * used for diagnostics only.
- */
-#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
-#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
- pointer. temp hold reg.
- diagnostics only. */
-#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
-#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
- pointer */
-
-/* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
-#define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */
-
-/* current state of all state machines in TX */
-#define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */
-#define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */
-#define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */
-#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine.
- = 0x01 when TX disabled. */
-#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */
-#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
- state machine */
-#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
-
-#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
-#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
-#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
-#define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */
-
-/* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
- * while the upper 23 bits are taken from the TX descriptor
- */
-#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
-#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
-
-/* 13 bit registers written by driver w/ descriptor value that follows
- * last valid xmit descriptor. kick # and complete # values are used by
- * the xmit dma engine to control tx descr fetching. if > 1 valid
- * tx descr is available within the cache line being read, cassini will
- * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
- */
-#define REG_TX_KICK0 0x2038 /* TX kick reg #1 */
-#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
-#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
-#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
-
-/* values of TX_COMPLETE_1-4 are written. each completion register
- * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
- * NOTE: completion reg values are only written back prior to TX_INTME and
- * TX_ALL interrupts. at all other times, the most up-to-date index values
- * should be obtained from the REG_TX_COMPLETE_# registers.
- * here's the layout:
- * offset from base addr completion # byte
- * 0 TX_COMPLETE_1_MSB
- * 1 TX_COMPLETE_1_LSB
- * 2 TX_COMPLETE_2_MSB
- * 3 TX_COMPLETE_2_LSB
- * 4 TX_COMPLETE_3_MSB
- * 5 TX_COMPLETE_3_LSB
- * 6 TX_COMPLETE_4_MSB
- * 7 TX_COMPLETE_4_LSB
- */
-#define TX_COMPWB_SIZE 8
-#define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back
- base low */
-#define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back
- base high */
-#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
-#define TX_COMPWB_MSB_SHIFT 0
-#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
-#define TX_COMPWB_LSB_SHIFT 8
-#define TX_COMPWB_NEXT(x) ((x) >> 16)
-
-/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
- * be 2KB-aligned. */
-#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
-#define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */
-#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
-#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
-
-/* 16-bit registers hold weights for the weighted round-robin of the
- * four CBQ TX descr rings. weights correspond to # bytes xferred from
- * host to TXFIFO in a round of WRR arbitration. can be set
- * dynamically with new weights set upon completion of the current
- * packet transfer from host memory to TXFIFO. a dummy write to any of
- * these registers causes a queue1 pre-emption with all historical bw
- * deficit data reset to 0 (useful when congestion requires a
- * pre-emption/re-allocation of network bandwidth
- */
-#define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */
-#define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */
-#define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */
-#define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */
-
-/* diagnostics access to any TX FIFO location. every access is 65
- * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
- * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
- * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
- * TX FIFO data integrity is desired, TX DMA should be
- * disabled. _DATA_HI_Tx should be the last access of the sequence.
- */
-#define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
-#define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
-#define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */
-#define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */
-#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
-#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
-
-/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
- * passed for the specified memory
- */
-#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
-#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
- controller state machine */
-#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
-#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
-#define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */
-#define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */
-#define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */
-#define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self
- clears on completion. */
-
-/** receive dma registers **/
-#define MAX_RX_DESC_RINGS 2
-#define MAX_RX_COMP_RINGS 4
-
-/* receive DMA channel configuration. default: 0x80910
- * free ring size = (1 << n)*32 -> [32 - 8k]
- * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
- * DEFAULT: 0x80910
- */
-#define REG_RX_CFG 0x4000 /* RX config */
-#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
- channel as soon as current
- frame xfer has completed.
- driver should disable MAC
- for 200ms before disabling
- RX */
-#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
- free desc ring.
- def: 0x8 = 8k */
-#define RX_CFG_DESC_RING_SHIFT 1
-#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
- ring. def: 0x8 = 32k */
-#define RX_CFG_COMP_RING_SHIFT 5
-#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
- batching. def: 0x0 =
- enabled */
-#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
- data byte of the packet
- w/in 8 byte boundares.
- this swivels the data
- DMA'ed to header
- buffers, jumbo buffers
- when header split is not
- requested and MTU sized
- buffers. def: 0x2 */
-#define RX_CFG_SWIVEL_SHIFT 10
-
-/* cassini+ only */
-#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
- RX free desc ring 2.
- def: 0x8 = 8k */
-#define RX_CFG_DESC_RING1_SHIFT 16
-
-
-/* the page size register allows cassini chips to do the following with
- * received data:
- * [--------------------------------------------------------------] page
- * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
- * |--------------| = PAGE_SIZE_BUFFER_STRIDE
- * page = PAGE_SIZE
- * offset = PAGE_SIZE_MTU_OFF
- * for the above example, MTU_BUFFER_COUNT = 4.
- * NOTE: as is apparent, you need to ensure that the following holds:
- * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
- * DEFAULT: 0x48002002 (8k pages)
- */
-#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
-#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
- by receive descriptors.
- if jumbo buffers are
- supported the page size
- should not be < 8k.
- 0b00 = 2k, 0b01 = 4k
- 0b10 = 8k, 0b11 = 16k
- DEFAULT: 8k */
-#define RX_PAGE_SIZE_SHIFT 0
-#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
- packs into a page.
- DEFAULT: 4 */
-#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
-#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
- each MTU buffer +
- offset from each
- other.
- 0b00 = 1k, 0b01 = 2k
- 0b10 = 4k, 0b11 = 8k
- DEFAULT: 0x1 */
-#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
-#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
- hw writes the MTU buffer
- into.
- 0b00 = 0,
- 0b01 = 64 bytes
- 0b10 = 96, 0b11 = 128
- DEFAULT: 0x1 */
-#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
-
-/* 11-bit counter points to next location in RX FIFO to be loaded/read.
- * shadow write pointers enable retries in case of early receive aborts.
- * DEFAULT: 0x0. generated on 64-bit boundaries.
- */
-#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
-#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
-#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
- pointer */
-#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
- pointer */
-#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
- pointer. (8-bit counter) */
-
-/* current state of RX DMA state engines + other info
- * DEFAULT: 0x0
- */
-#define REG_RX_DEBUG 0x401C /* RX debug */
-#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC:
- 0x0 = idle, 0x1 = load_bop
- 0x2 = load 1, 0x3 = load 2
- 0x4 = load 3, 0x5 = load 4
- 0x6 = last detect
- 0x7 = wait req
- 0x8 = wait req statuss 1st
- 0x9 = load st
- 0xa = bubble mac
- 0xb = error */
-#define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and
- RX FIFO:
- 0x0 = idle, 0x1 = hp xfr
- 0x2 = wait hp ready
- 0x3 = wait flow code
- 0x4 = fifo xfer
- 0x5 = make status
- 0x6 = csum ready
- 0x7 = error */
-#define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine
- w/ MAC:
- 0x0 = idle
- 0x1 = wait xoff ack
- 0x2 = wait xon
- 0x3 = wait xon ack */
-#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
- states:
- 0x0 = idle data
- 0x1 = header begin
- 0x2 = xfer header
- 0x3 = xfer header ld
- 0x4 = mtu begin
- 0x5 = xfer mtu
- 0x6 = xfer mtu ld
- 0x7 = jumbo begin
- 0x8 = xfer jumbo
- 0x9 = xfer jumbo ld
- 0xa = reas begin
- 0xb = xfer reas
- 0xc = flush tag
- 0xd = xfer reas ld
- 0xe = error
- 0xf = bubble idle */
-#define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine
- states:
- 0x0 = idle desc
- 0x1 = wait ack
- 0x9 = wait ack 2
- 0x2 = fetch desc 1
- 0xa = fetch desc 2
- 0x3 = load ptrs
- 0x4 = wait dma
- 0x5 = wait ack batch
- 0x6 = post batch
- 0x7 = xfr done */
-#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
- interrupt queue */
-#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer
- of the interrupt queue */
-
-/* flow control frames are emitted using two PAUSE thresholds:
- * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
- * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
- * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
- * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
- * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
- * value is is 0x6F.
- * DEFAULT: 0x00078
- */
-#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
-#define RX_PAUSE_THRESH_QUANTUM 64
-#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
- RX FIFO occupancy >
- value*64B */
-#define RX_PAUSE_THRESH_OFF_SHIFT 0
-#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
- emitting XOFF PAUSE when RX
- FIFO occupancy falls below
- this value*64B. must be
- < XOFF threshold. if =
- RX_FIFO_SIZE< XON frames are
- never emitted. */
-#define RX_PAUSE_THRESH_ON_SHIFT 12
-
-/* 13-bit register used to control RX desc fetching and intr generation. if 4+
- * valid RX descriptors are available, Cassini will read 4 at a time.
- * writing N means that all desc up to *but* excluding N are available. N must
- * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
- * DEFAULT: 0 on reset
- */
-#define REG_RX_KICK 0x4024 /* RX kick reg */
-
-/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
- * lower 13 bits of the low register are hard-wired to 0.
- */
-#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
- base low */
-#define REG_RX_DB_HI 0x402C /* RX descriptor ring
- base hi */
-#define REG_RX_CB_LOW 0x4030 /* RX completion ring
- base low */
-#define REG_RX_CB_HI 0x4034 /* RX completion ring
- base hi */
-/* 13-bit register indicate desc used by cassini for receive frames. used
- * for diagnostic purposes.
- * DEFAULT: 0 on reset
- */
-#define REG_RX_COMP 0x4038 /* (ro) RX completion */
-
-/* HEAD and TAIL are used to control RX desc posting and interrupt
- * generation. hw moves the head register to pass ownership to sw. sw
- * moves the tail register to pass ownership back to hw. to give all
- * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
- * more entries are available, DMA will pause and an interrupt will be
- * generated to indicate no more entries are available. sw can use
- * this interrupt to reduce the # of times it must update the
- * completion tail register.
- * DEFAULT: 0 on reset
- */
-#define REG_RX_COMP_HEAD 0x403C /* RX completion head */
-#define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
-
-/* values used for receive interrupt blanking. loaded each time the ISR is read
- * DEFAULT: 0x00000000
- */
-#define REG_RX_BLANK 0x4044 /* RX blanking register
- for ISR read */
-#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
- this many sets of completion
- writebacks (up to 2 packets)
- occur since the last time
- the ISR was read. 0 = no
- packet blanking */
-#define RX_BLANK_INTR_PKT_SHIFT 0<