diff options
| author | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
| commit | 6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch) | |
| tree | df0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/cassini.h | |
| parent | 7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff) | |
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cassini.h')
| -rw-r--r-- | drivers/net/cassini.h | 766 |
1 files changed, 383 insertions, 383 deletions
diff --git a/drivers/net/cassini.h b/drivers/net/cassini.h index ab55c7ee101..a970804487c 100644 --- a/drivers/net/cassini.h +++ b/drivers/net/cassini.h @@ -21,7 +21,7 @@ * * vendor id: 0x108E (Sun Microsystems, Inc.) * device id: 0xabba (Cassini) - * revision ids: 0x01 = Cassini + * revision ids: 0x01 = Cassini * 0x02 = Cassini rev 2 * 0x10 = Cassini+ * 0x11 = Cassini+ 0.2u @@ -46,16 +46,16 @@ * appear in cassini+. REG_MINUS_ addresses only appear in cassini. */ #define CAS_ID_REV2 0x02 -#define CAS_ID_REVPLUS 0x10 -#define CAS_ID_REVPLUS02u 0x11 +#define CAS_ID_REVPLUS 0x10 +#define CAS_ID_REVPLUS02u 0x11 #define CAS_ID_REVSATURNB2 0x30 /** global resources **/ /* this register sets the weights for the weighted round robin arbiter. e.g., * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit - * for its next turn to access the pci bus. - * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 + * for its next turn to access the pci bus. + * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 * DEFAULT: 0x0, SIZE: 5 bits */ #define REG_CAWR 0x0004 /* core arbitration weight */ @@ -66,8 +66,8 @@ #define CAWR_RR_DIS 0x10 /* [4] */ /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst - * sizes determined by length of packet or descriptor transfer and the - * max length allowed by the target. + * sizes determined by length of packet or descriptor transfer and the + * max length allowed by the target. * DEFAULT: 0x0, SIZE: 1 bit */ #define REG_INF_BURST 0x0008 /* infinite burst enable reg */ @@ -75,21 +75,21 @@ /* top level interrupts [0-9] are auto-cleared to 0 when the status * register is read. second level interrupts [13 - 18] are cleared at - * the source. tx completion register 3 is replicated in [19 - 31] + * the source. tx completion register 3 is replicated in [19 - 31] * DEFAULT: 0x00000000, SIZE: 29 bits */ #define REG_INTR_STATUS 0x000C /* interrupt status register */ -#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set +#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set xferred from host queue to TX FIFO */ #define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into TX FIFO. i.e., - TX Kick == TX complete. if + TX Kick == TX complete. if PACED_MODE set, then TX FIFO also empty */ -#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx +#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx FIFO */ -#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing +#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing corrupted. FATAL ERROR */ #define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred from RX FIFO to host mem. @@ -98,18 +98,18 @@ intr blanking. */ #define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers. RX Kick == RX complete */ -#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing +#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing corrupted. FATAL ERROR */ #define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion ring to post descriptors. RX complete head incr to almost reach RX complete tail */ -#define INTR_RX_BUF_AE 0x00000100 /* less than the +#define INTR_RX_BUF_AE 0x00000100 /* less than the programmable threshold # of free descr avail for hw use */ -#define INTR_RX_COMP_AF 0x00000200 /* less than the +#define INTR_RX_COMP_AF 0x00000200 /* less than the programmable threshold # of descr spaces for hw use in completion descr @@ -119,17 +119,17 @@ from fifo during DMA or header parser provides TCP header and payload size > - MAC packet size. + MAC packet size. FATAL ERROR */ #define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this - bit will be set if an interrupt + bit will be set if an interrupt generated on the pci bus. useful - when driver is polling for + when driver is polling for interrupts */ #define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */ -#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at +#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at least 1 unmasked interrupt set */ -#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at +#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at least 1 unmasked interrupt set */ #define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has at least 1 unmasked interrupt @@ -137,9 +137,9 @@ #define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least 1 unmasked interrupt set */ #define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the - BIF has at least 1 unmasked + BIF has at least 1 unmasked interrupt set */ -#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion +#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion 3 reg data */ #define INTR_TX_COMP_3_SHIFT 19 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \ @@ -149,7 +149,7 @@ INTR_MAC_CTRL_STATUS) /* determines which status events will cause an interrupt. layout same - * as REG_INTR_STATUS. + * as REG_INTR_STATUS. * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits */ #define REG_INTR_MASK 0x0010 /* Interrupt mask */ @@ -158,18 +158,18 @@ * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. * DEFAULT: 0x00000000, SIZE: 12 bits */ -#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask +#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask (used w/ status alias) */ /* same as REG_INTR_STATUS except that only bits cleared are those selected by - * REG_ALIAS_CLEAR + * REG_ALIAS_CLEAR * DEFAULT: 0x00000000, SIZE: 29 bits */ -#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias +#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias (selective clear) */ /* DEFAULT: 0x0, SIZE: 3 bits */ #define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */ -#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. +#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. set if no ACK64# during ABS64 cycle in Cassini. */ #define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if @@ -179,16 +179,16 @@ unused in Cassini. */ #define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req. unused in Cassini. */ -#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during +#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during DMA. unused in cassini. */ /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event - * causes an interrupt to be generated. + * causes an interrupt to be generated. * DEFAULT: 0x7, SIZE: 3 bits */ #define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */ -/* used to configure PCI related parameters that are not in PCI config space. +/* used to configure PCI related parameters that are not in PCI config space. * DEFAULT: 0bxx000, SIZE: 5 bits */ #define REG_BIM_CFG 0x1008 /* BIM Configuration */ @@ -201,7 +201,7 @@ #define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */ #define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */ #define BIM_CFG_RESERVED2 0x100 /* reserved */ -#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global +#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global reset. reserved in Cassini. */ #define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended. reserved in Cassini. */ @@ -212,7 +212,7 @@ #define REG_BIM_DIAG 0x100C /* BIM Diagnostic */ #define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state machine bits [21:0] */ -#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state +#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state machine bits [6:0] */ /* writing to SW_RESET_TX and SW_RESET_RX will issue a global @@ -224,14 +224,14 @@ #define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until cleared to 0. */ #define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low). - resets PHY and anything else + resets PHY and anything else connected to RSTOUT#. RSTOUT# is also activated by local PCI - reset when hot-swap is being + reset when hot-swap is being done. */ -#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with - this bit set, PCS and SLINK - modules won't be reset. +#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with + this bit set, PCS and SLINK + modules won't be reset. i.e., link won't drop. */ #define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */ #define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits: @@ -252,7 +252,7 @@ 0b01: AD_ACK_RX 0b10: AD_ACK_TX 0b11: AD_IDL_TX */ -#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits +#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits 0b00: WR_PCI_WAT 0b01: WR_PCI_RDY 0b11: WR_PCI_ACK */ @@ -268,7 +268,7 @@ * value written has both lower and upper 32-bit halves rotated to the right * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF */ -#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test +#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test Cassini+: reserved */ /* output enables are provided for each device's chip select and for the rest @@ -276,12 +276,12 @@ * bits are connected to general purpus control/status bits. * DEFAULT: 0x7 */ -#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device +#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device output EN. default: 0x7 */ #define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and OE signal output enable on the local bus interface. these - are shared between both local + are shared between both local bus devices. tristate when 0. */ #define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */ #define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip @@ -291,8 +291,8 @@ #define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */ /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR - * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. - * _DATA_HI should be the last access of the sequence. + * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. + * _DATA_HI should be the last access of the sequence. * DEFAULT: undefined */ #define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for @@ -304,10 +304,10 @@ #define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */ #define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */ -/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. +/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. * bit auto-clears when done with status read from _SUMMARY and _PASS bits. */ -#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST +#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST control/status */ #define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */ #define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer. @@ -321,7 +321,7 @@ #define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */ #define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */ #define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST. - Cassini only. reserved in + Cassini only. reserved in Cassini+. */ #define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST. Cassini only. reserved in @@ -333,7 +333,7 @@ #define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux select register */ -/* enable probe monitoring mode and select data appearing on the P_A* bus. bit +/* enable probe monitoring mode and select data appearing on the P_A* bus. bit * values for _SEL_HI_MASK and _SEL_LOW_MASK: * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w, * wtc empty r, post pci) @@ -353,7 +353,7 @@ * 0xe: hp probe[7:0] 0xf: mac probe[7:0] */ #define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */ -#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be +#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be driven on local bus P_A[15:0] for debugging */ #define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals: @@ -362,28 +362,28 @@ 0x30 = tx[1:0] 0xC0 = hp[1:0] */ #define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear - on P_A[15:8]. see above for + on P_A[15:8]. see above for values. */ #define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear - on P_A[7:0]. see above for + on P_A[7:0]. see above for values. */ -/* values mean the same thing as REG_INTR_MASK excep that it's for INTB. +/* values mean the same thing as REG_INTR_MASK excep that it's for INTB. DEFAULT: 0x1F */ #define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask register 2 for INTB */ #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16) -/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to - * all of the alternate (2-4) INTR registers while _1 corresponds to only - * _MASK_1 and _STATUS_1 registers. +/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to + * all of the alternate (2-4) INTR registers while _1 corresponds to only + * _MASK_1 and _STATUS_1 registers. * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers */ -#define INTR_RX_DONE_ALT 0x01 +#define INTR_RX_DONE_ALT 0x01 #define INTR_RX_COMP_FULL_ALT 0x02 #define INTR_RX_COMP_AF_ALT 0x04 #define INTR_RX_BUF_UNAVAIL_1 0x08 #define INTR_RX_BUF_AE_1 0x10 /* almost empty */ -#define INTRN_MASK_RX_EN 0x80 +#define INTRN_MASK_RX_EN 0x80 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \ INTR_RX_COMP_FULL_ALT | \ INTR_RX_COMP_AF_ALT | \ @@ -399,7 +399,7 @@ register 2 for INTB */ #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16) -#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status +#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status register alias 2 for INTB */ #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16) @@ -411,18 +411,18 @@ #define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */ #define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */ #define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */ -#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode. +#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode. 0 = normal */ -#define SATURN_PCFG_MTP 0x00000080 /* test point select */ -#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 = +#define SATURN_PCFG_MTP 0x00000080 /* test point select */ +#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 = GMII on SERDES pins for monitoring. */ #define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all pins configed as outputs. for power saving when using internal phy. */ -#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl - polarity from strapping +#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl + polarity from strapping value. 1 = mac core led ctrl polarity active low. */ @@ -433,26 +433,26 @@ #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT) #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1) -/* TX configuration. - * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 +/* TX configuration. + * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 * DEFAULT: 0x3F000001 */ #define REG_TX_CFG 0x2004 /* TX config */ #define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA will stop after xfer of current buffer has been completed. */ -#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be - accessed w/ FIFO addr - and data registers. - TX DMA should be +#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be + accessed w/ FIFO addr + and data registers. + TX DMA should be disabled. */ #define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in ring 1. */ #define TX_CFG_DESC_RING0_SHIFT 2 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4) #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4) -#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after - TX FIFO becomes empty. +#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after + TX FIFO becomes empty. if 0, TX_ALL set if descr queue empty. */ #define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */ @@ -470,26 +470,26 @@ through Q4 */ #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion writeback */ -#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port +#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port connection - 0b00: tx mac req, + 0b00: tx mac req, tx mac retry req, tx ack and tx tag. - 0b01: txdma rd req, + 0b01: txdma rd req, txdma rd ack, txdma rd rdy, txdma rd type0 - 0b11: txdma wr req, + 0b11: txdma wr req, txdma wr ack, txdma wr rdy, txdma wr xfr done. */ #define TX_CFG_CTX_SEL_SHIFT 30 - + /* 11-bit counters that point to next location in FIFO to be loaded/retrieved. * used for diagnostics only. */ #define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */ -#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write +#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write pointer. temp hold reg. diagnostics only. */ #define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */ @@ -509,7 +509,7 @@ #define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller state machine */ #define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */ - + #define REG_TX_SM_2 0x202C /* TX state machine reg #2 */ #define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */ #define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */ @@ -521,9 +521,9 @@ #define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */ #define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ -/* 13 bit registers written by driver w/ descriptor value that follows +/* 13 bit registers written by driver w/ descriptor value that follows * last valid xmit descriptor. kick # and complete # values are used by - * the xmit dma engine to control tx descr fetching. if > 1 valid + * the xmit dma engine to control tx descr fetching. if > 1 valid * tx descr is available within the cache line being read, cassini will * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro. */ @@ -532,12 +532,12 @@ #define REG_TX_COMP0 0x2048 /* TX completion reg #1 */ #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4) -/* values of TX_COMPLETE_1-4 are written. each completion register - * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. +/* values of TX_COMPLETE_1-4 are written. each completion register + * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. * NOTE: completion reg values are only written back prior to TX_INTME and - * TX_ALL interrupts. at all other times, the most up-to-date index values - * should be obtained from the REG_TX_COMPLETE_# registers. - * here's the layout: + * TX_ALL interrupts. at all other times, the most up-to-date index values + * should be obtained from the REG_TX_COMPLETE_# registers. + * here's the layout: * offset from base addr completion # byte * 0 TX_COMPLETE_1_MSB * 1 TX_COMPLETE_1_LSB @@ -558,7 +558,7 @@ #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL #define TX_COMPWB_LSB_SHIFT 8 #define TX_COMPWB_NEXT(x) ((x) >> 16) - + /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must * be 2KB-aligned. */ #define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */ @@ -594,11 +594,11 @@ #define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */ #define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */ -/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST +/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST * passed for the specified memory */ #define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */ -#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST +#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST controller state machine */ #define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */ #define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */ @@ -612,33 +612,33 @@ #define MAX_RX_DESC_RINGS 2 #define MAX_RX_COMP_RINGS 4 -/* receive DMA channel configuration. default: 0x80910 +/* receive DMA channel configuration. default: 0x80910 * free ring size = (1 << n)*32 -> [32 - 8k] - * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 + * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 * DEFAULT: 0x80910 */ #define REG_RX_CFG 0x4000 /* RX config */ #define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops channel as soon as current frame xfer has completed. - driver should disable MAC - for 200ms before disabling + driver should disable MAC + for 200ms before disabling RX */ -#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX - free desc ring. +#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX + free desc ring. def: 0x8 = 8k */ #define RX_CFG_DESC_RING_SHIFT 1 #define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete ring. def: 0x8 = 32k */ #define RX_CFG_COMP_RING_SHIFT 5 -#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc +#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc batching. def: 0x0 = enabled */ -#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st - data byte of the packet +#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st + data byte of the packet w/in 8 byte boundares. - this swivels the data - DMA'ed to header + this swivels the data + DMA'ed to header buffers, jumbo buffers when header split is not requested and MTU sized @@ -647,17 +647,17 @@ /* cassini+ only */ #define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in - RX free desc ring 2. + RX free desc ring 2. def: 0x8 = 8k */ #define RX_CFG_DESC_RING1_SHIFT 16 -/* the page size register allows cassini chips to do the following with +/* the page size register allows cassini chips to do the following with * received data: * [--------------------------------------------------------------] page * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad] * |--------------| = PAGE_SIZE_BUFFER_STRIDE - * page = PAGE_SIZE + * page = PAGE_SIZE * offset = PAGE_SIZE_MTU_OFF * for the above example, MTU_BUFFER_COUNT = 4. * NOTE: as is apparent, you need to ensure that the following holds: @@ -667,20 +667,20 @@ #define REG_RX_PAGE_SIZE 0x4004 /* RX page size */ #define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to by receive descriptors. - if jumbo buffers are - supported the page size + if jumbo buffers are + supported the page size should not be < 8k. 0b00 = 2k, 0b01 = 4k 0b10 = 8k, 0b11 = 16k DEFAULT: 8k */ #define RX_PAGE_SIZE_SHIFT 0 #define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw - packs into a page. + packs into a page. DEFAULT: 4 */ #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11 #define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate - each MTU buffer + - offset from each + each MTU buffer + + offset from each other. 0b00 = 1k, 0b01 = 2k 0b10 = 4k, 0b11 = 8k @@ -688,24 +688,24 @@ #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27 #define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that hw writes the MTU buffer - into. - 0b00 = 0, + into. + 0b00 = 0, 0b01 = 64 bytes 0b10 = 96, 0b11 = 128 DEFAULT: 0x1 */ #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30 - -/* 11-bit counter points to next location in RX FIFO to be loaded/read. + +/* 11-bit counter points to next location in RX FIFO to be loaded/read. * shadow write pointers enable retries in case of early receive aborts. * DEFAULT: 0x0. generated on 64-bit boundaries. */ #define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */ #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */ -#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write +#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write pointer */ #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read pointer */ -#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read +#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read pointer. (8-bit counter) */ /* current state of RX DMA state engines + other info @@ -738,7 +738,7 @@ 0x2 = wait xon 0x3 = wait xon ack */ #define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine - states: + states: 0x0 = idle data 0x1 = header begin 0x2 = xfer header @@ -747,7 +747,7 @@ 0x5 = xfer mtu 0x6 = xfer mtu ld 0x7 = jumbo begin - 0x8 = xfer jumbo + 0x8 = xfer jumbo 0x9 = xfer jumbo ld 0xa = reas begin 0xb = xfer reas @@ -776,15 +776,15 @@ * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes. * PAUSE thresholds defined in terms of FIFO occupancy and may be translated - * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames + * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max - * value is is 0x6F. + * value is is 0x6F. * DEFAULT: 0x00078 */ #define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */ #define RX_PAUSE_THRESH_QUANTUM 64 #define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when - RX FIFO occupancy > + RX FIFO occupancy > value*64B */ #define RX_PAUSE_THRESH_OFF_SHIFT 0 #define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after @@ -797,9 +797,9 @@ #define RX_PAUSE_THRESH_ON_SHIFT 12 /* 13-bit register used to control RX desc fetching and intr generation. if 4+ - * valid RX descriptors are available, Cassini will read 4 at a time. + * valid RX descriptors are available, Cassini will read 4 at a time. * writing N means that all desc up to *but* excluding N are available. N must - * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. + * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. * DEFAULT: 0 on reset */ #define REG_RX_KICK 0x4024 /* RX kick reg */ @@ -807,16 +807,16 @@ /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings. * lower 13 bits of the low register are hard-wired to 0. */ -#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring +#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring base low */ #define REG_RX_DB_HI 0x402C /* RX descriptor ring base hi */ #define REG_RX_CB_LOW 0x4030 /* RX completion ring base low */ -#define REG_RX_CB_HI 0x4034 /* RX completion ring +#define REG_RX_CB_HI 0x4034 /* RX completion ring base hi */ /* 13-bit register indicate desc used by cassini for receive frames. used - * for diagnostic purposes. + * for diagnostic purposes. * DEFAULT: 0 on reset */ #define REG_RX_COMP 0x4038 /* (ro) RX completion */ @@ -837,9 +837,9 @@ /* values used for receive interrupt blanking. loaded each time the ISR is read * DEFAULT: 0x00000000 */ -#define REG_RX_BLANK 0x4044 /* RX blanking register +#define REG_RX_BLANK 0x4044 /* RX blanking register for ISR read */ -#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if +#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if this many sets of completion writebacks (up to 2 packets) occur since the last time @@ -849,33 +849,33 @@ #define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted if that many clocks were counted since last time the - ISR was read. + ISR was read. each count is 512 core clocks (125MHz). 0 = no time blanking */ #define RX_BLANK_INTR_TIME_SHIFT 12 -/* values used for interrupt generation based on threshold values of how +/* values used for interrupt generation based on threshold values of how * many free desc and completion entries are available for hw use. * DEFAULT: 0x00000000 */ -#define REG_RX_AE_THRESH 0x4048 /* RX almost empty +#define REG_RX_AE_THRESH 0x4048 /* RX almost empty thresholds */ -#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be +#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be generated if # desc - avail for hw use <= + avail for hw use <= # */ #define RX_AE_THRESH_FREE_SHIFT 0 #define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be - generated if # of + generated if # of completion entries - avail for hw use <= + avail for hw use <= # */ #define RX_AE_THRESH_COMP_SHIFT 13 -/* probabilities for random early drop (RED) thresholds on a FIFO threshold - * basis. probability should increase when the FIFO level increases. control - * packets are never dropped and not counted in stats. probability programmed +/* probabilities for random early drop (RED) thresholds on a FIFO threshold + * basis. probability should increase when the FIFO level increases. control + * packets are never dropped and not counted in stats. probability programmed * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped. * DEFAULT: 0x00000000 */ @@ -885,8 +885,8 @@ #define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */ #define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */ -/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. - * RX control FIFO = # of packets in RX FIFO. +/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. + * RX control FIFO = # of packets in RX FIFO. * DEFAULT: 0x0 */ #define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */ @@ -895,12 +895,12 @@ #define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */ #define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */ #define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */ -#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr +#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr high */ /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST * START/COMPLETE is writeable. START will clear when the BIST has completed - * checking all 17 RAMS. + * checking all 17 RAMS. * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0 */ #define REG_RX_BIST 0x4060 /* (ro) RX BIST */ @@ -923,41 +923,41 @@ #define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */ #define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */ #define RX_BIST_SUMMARY 0x00000002 /* when BIST complete, - summary pass bit + summary pass bit contains AND of BIST results of all 16 RAMS */ -#define RX_BIST_START 0x00000001 /* write 1 to start +#define RX_BIST_START 0x00000001 /* write 1 to start BIST. self clears on completion. */ /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read - * from to retrieve packet control info. + * from to retrieve packet control info. * DEFAULT: 0 */ -#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO +#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO write ptr */ #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read ptr */ /* receive interrupt blanking. loaded each time interrupt alias register is - * read. + * read. * DEFAULT: 0x0 */ #define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for alias read */ -#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if # - completion writebacks - > # since last ISR - read. 0 = no - blanking. up to 2 - packets per +#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if # + completion writebacks + > # since last ISR + read. 0 = no + blanking. up to 2 + packets per completion wb. */ #define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if # clocks > # since last ISR read. each count is 512 core clocks - (125MHz). 0 = no + (125MHz). 0 = no blanking. */ /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed @@ -981,13 +981,13 @@ * should be last write access of the write sequence. * DEFAULT: undefined */ -#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and +#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and Batching FIFO addr */ -#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data +#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data low */ -#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data +#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data mid */ -#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data +#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data hi and flow id */ #define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */ #define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */ @@ -1004,7 +1004,7 @@ T1 */ /* 64-bit pointer to receive data buffer in host memory used for headers and - * small packets. MSB in high register. loaded by DMA state machine and + * small packets. MSB in high register. loaded by DMA state machine and * increments as DMA writes receive data. only 50 LSB are incremented. top< |