broadcom: Move the Broadcom drivers

Moves the drivers for Broadcom devices into
drivers/net/ethernet/broadcom/ and the necessary Kconfig and Makefile
changes.

CC: Eilon Greenstein <eilong@broadcom.com>
CC: Michael Chan <mchan@broadcom.com>
CC: Matt Carlson <mcarlson@broadcom.com>
CC: Gary Zambrano <zambrano@broadcom.com>
CC: "Maciej W. Rozycki" <macro@linux-mips.org>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

21 files changed, 0 insertions, 60972 deletions

diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile
deleted file mode 100644
index 48fbdd48f88..00000000000
--- a/drivers/net/bnx2x/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for Broadcom 10-Gigabit ethernet driver
-#
-
-obj-$(CONFIG_BNX2X) += bnx2x.o
-
-bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
deleted file mode 100644
index c423504a755..00000000000
--- a/drivers/net/bnx2x/bnx2x.h
+++ /dev/null
@@ -1,2014 +0,0 @@
-/* bnx2x.h: Broadcom Everest network driver.
- *
- * Copyright (c) 2007-2011 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- *
- * Maintained by: Eilon Greenstein <eilong@broadcom.com>
- * Written by: Eliezer Tamir
- * Based on code from Michael Chan's bnx2 driver
- */
-
-#ifndef BNX2X_H
-#define BNX2X_H
-#include <linux/netdevice.h>
-#include <linux/dma-mapping.h>
-#include <linux/types.h>
-
-/* compilation time flags */
-
-/* define this to make the driver freeze on error to allow getting debug info
- * (you will need to reboot afterwards) */
-/* #define BNX2X_STOP_ON_ERROR */
-
-#define DRV_MODULE_VERSION      "1.70.00-0"
-#define DRV_MODULE_RELDATE      "2011/06/13"
-#define BNX2X_BC_VER            0x040200
-
-#if defined(CONFIG_DCB)
-#define BCM_DCBNL
-#endif
-#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
-#define BCM_CNIC 1
-#include "../cnic_if.h"
-#endif
-
-#ifdef BCM_CNIC
-#define BNX2X_MIN_MSIX_VEC_CNT 3
-#define BNX2X_MSIX_VEC_FP_START 2
-#else
-#define BNX2X_MIN_MSIX_VEC_CNT 2
-#define BNX2X_MSIX_VEC_FP_START 1
-#endif
-
-#include <linux/mdio.h>
-
-#include "bnx2x_reg.h"
-#include "bnx2x_fw_defs.h"
-#include "bnx2x_hsi.h"
-#include "bnx2x_link.h"
-#include "bnx2x_sp.h"
-#include "bnx2x_dcb.h"
-#include "bnx2x_stats.h"
-
-/* error/debug prints */
-
-#define DRV_MODULE_NAME		"bnx2x"
-
-/* for messages that are currently off */
-#define BNX2X_MSG_OFF			0
-#define BNX2X_MSG_MCP			0x010000 /* was: NETIF_MSG_HW */
-#define BNX2X_MSG_STATS			0x020000 /* was: NETIF_MSG_TIMER */
-#define BNX2X_MSG_NVM			0x040000 /* was: NETIF_MSG_HW */
-#define BNX2X_MSG_DMAE			0x080000 /* was: NETIF_MSG_HW */
-#define BNX2X_MSG_SP			0x100000 /* was: NETIF_MSG_INTR */
-#define BNX2X_MSG_FP			0x200000 /* was: NETIF_MSG_INTR */
-
-#define DP_LEVEL			KERN_NOTICE	/* was: KERN_DEBUG */
-
-/* regular debug print */
-#define DP(__mask, __fmt, __args...)				\
-do {								\
-	if (bp->msg_enable & (__mask))				\
-		printk(DP_LEVEL "[%s:%d(%s)]" __fmt,		\
-		       __func__, __LINE__,			\
-		       bp->dev ? (bp->dev->name) : "?",		\
-		       ##__args);				\
-} while (0)
-
-#define DP_CONT(__mask, __fmt, __args...)			\
-do {								\
-	if (bp->msg_enable & (__mask))				\
-		pr_cont(__fmt, ##__args);			\
-} while (0)
-
-/* errors debug print */
-#define BNX2X_DBG_ERR(__fmt, __args...)				\
-do {								\
-	if (netif_msg_probe(bp))				\
-		pr_err("[%s:%d(%s)]" __fmt,			\
-		       __func__, __LINE__,			\
-		       bp->dev ? (bp->dev->name) : "?",		\
-		       ##__args);				\
-} while (0)
-
-/* for errors (never masked) */
-#define BNX2X_ERR(__fmt, __args...)				\
-do {								\
-	pr_err("[%s:%d(%s)]" __fmt,				\
-	       __func__, __LINE__,				\
-	       bp->dev ? (bp->dev->name) : "?",			\
-	       ##__args);					\
-	} while (0)
-
-#define BNX2X_ERROR(__fmt, __args...) do { \
-	pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
-	} while (0)
-
-
-/* before we have a dev->name use dev_info() */
-#define BNX2X_DEV_INFO(__fmt, __args...)			 \
-do {								 \
-	if (netif_msg_probe(bp))				 \
-		dev_info(&bp->pdev->dev, __fmt, ##__args);	 \
-} while (0)
-
-#define BNX2X_MAC_FMT		"%pM"
-#define BNX2X_MAC_PRN_LIST(mac)	(mac)
-
-
-#ifdef BNX2X_STOP_ON_ERROR
-void bnx2x_int_disable(struct bnx2x *bp);
-#define bnx2x_panic() do { \
-		bp->panic = 1; \
-		BNX2X_ERR("driver assert\n"); \
-		bnx2x_int_disable(bp); \
-		bnx2x_panic_dump(bp); \
-	} while (0)
-#else
-#define bnx2x_panic() do { \
-		bp->panic = 1; \
-		BNX2X_ERR("driver assert\n"); \
-		bnx2x_panic_dump(bp); \
-	} while (0)
-#endif
-
-#define bnx2x_mc_addr(ha)      ((ha)->addr)
-#define bnx2x_uc_addr(ha)      ((ha)->addr)
-
-#define U64_LO(x)			(u32)(((u64)(x)) & 0xffffffff)
-#define U64_HI(x)			(u32)(((u64)(x)) >> 32)
-#define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))
-
-
-#define REG_ADDR(bp, offset)		((bp->regview) + (offset))
-
-#define REG_RD(bp, offset)		readl(REG_ADDR(bp, offset))
-#define REG_RD8(bp, offset)		readb(REG_ADDR(bp, offset))
-#define REG_RD16(bp, offset)		readw(REG_ADDR(bp, offset))
-
-#define REG_WR(bp, offset, val)		writel((u32)val, REG_ADDR(bp, offset))
-#define REG_WR8(bp, offset, val)	writeb((u8)val, REG_ADDR(bp, offset))
-#define REG_WR16(bp, offset, val)	writew((u16)val, REG_ADDR(bp, offset))
-
-#define REG_RD_IND(bp, offset)		bnx2x_reg_rd_ind(bp, offset)
-#define REG_WR_IND(bp, offset, val)	bnx2x_reg_wr_ind(bp, offset, val)
-
-#define REG_RD_DMAE(bp, offset, valp, len32) \
-	do { \
-		bnx2x_read_dmae(bp, offset, len32);\
-		memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
-	} while (0)
-
-#define REG_WR_DMAE(bp, offset, valp, len32) \
-	do { \
-		memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
-		bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
-				 offset, len32); \
-	} while (0)
-
-#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
-	REG_WR_DMAE(bp, offset, valp, len32)
-
-#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
-	do { \
-		memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
-		bnx2x_write_big_buf_wb(bp, addr, len32); \
-	} while (0)
-
-#define SHMEM_ADDR(bp, field)		(bp->common.shmem_base + \
-					 offsetof(struct shmem_region, field))
-#define SHMEM_RD(bp, field)		REG_RD(bp, SHMEM_ADDR(bp, field))
-#define SHMEM_WR(bp, field, val)	REG_WR(bp, SHMEM_ADDR(bp, field), val)
-
-#define SHMEM2_ADDR(bp, field)		(bp->common.shmem2_base + \
-					 offsetof(struct shmem2_region, field))
-#define SHMEM2_RD(bp, field)		REG_RD(bp, SHMEM2_ADDR(bp, field))
-#define SHMEM2_WR(bp, field, val)	REG_WR(bp, SHMEM2_ADDR(bp, field), val)
-#define MF_CFG_ADDR(bp, field)		(bp->common.mf_cfg_base + \
-					 offsetof(struct mf_cfg, field))
-#define MF2_CFG_ADDR(bp, field)		(bp->common.mf2_cfg_base + \
-					 offsetof(struct mf2_cfg, field))
-
-#define MF_CFG_RD(bp, field)		REG_RD(bp, MF_CFG_ADDR(bp, field))
-#define MF_CFG_WR(bp, field, val)	REG_WR(bp,\
-					       MF_CFG_ADDR(bp, field), (val))
-#define MF2_CFG_RD(bp, field)		REG_RD(bp, MF2_CFG_ADDR(bp, field))
-
-#define SHMEM2_HAS(bp, field)		((bp)->common.shmem2_base &&	\
-					 (SHMEM2_RD((bp), size) >	\
-					 offsetof(struct shmem2_region, field)))
-
-#define EMAC_RD(bp, reg)		REG_RD(bp, emac_base + reg)
-#define EMAC_WR(bp, reg, val)		REG_WR(bp, emac_base + reg, val)
-
-/* SP SB indices */
-
-/* General SP events - stats query, cfc delete, etc  */
-#define HC_SP_INDEX_ETH_DEF_CONS		3
-
-/* EQ completions */
-#define HC_SP_INDEX_EQ_CONS			7
-
-/* FCoE L2 connection completions */
-#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS		6
-#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS		4
-/* iSCSI L2 */
-#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS		5
-#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS	1
-
-/* Special clients parameters */
-
-/* SB indices */
-/* FCoE L2 */
-#define BNX2X_FCOE_L2_RX_INDEX \
-	(&bp->def_status_blk->sp_sb.\
-	index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
-
-#define BNX2X_FCOE_L2_TX_INDEX \
-	(&bp->def_status_blk->sp_sb.\
-	index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
-
-/**
- *  CIDs and CLIDs:
- *  CLIDs below is a CLID for func 0, then the CLID for other
- *  functions will be calculated by the formula:
- *
- *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
- *
- */
-/* iSCSI L2 */
-#define BNX2X_ISCSI_ETH_CL_ID_IDX	1
-#define BNX2X_ISCSI_ETH_CID		49
-
-/* FCoE L2 */
-#define BNX2X_FCOE_ETH_CL_ID_IDX	2
-#define BNX2X_FCOE_ETH_CID		50
-
-/** Additional rings budgeting */
-#ifdef BCM_CNIC
-#define CNIC_PRESENT			1
-#define FCOE_PRESENT			1
-#else
-#define CNIC_PRESENT			0
-#define FCOE_PRESENT			0
-#endif /* BCM_CNIC */
-#define NON_ETH_CONTEXT_USE	(FCOE_PRESENT)
-
-#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
-	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
-
-#define SM_RX_ID			0
-#define SM_TX_ID			1
-
-/* defines for multiple tx priority indices */
-#define FIRST_TX_ONLY_COS_INDEX		1
-#define FIRST_TX_COS_INDEX		0
-
-/* defines for decodeing the fastpath index and the cos index out of the
- * transmission queue index
- */
-#define MAX_TXQS_PER_COS	FP_SB_MAX_E1x
-
-#define TXQ_TO_FP(txq_index)	((txq_index) % MAX_TXQS_PER_COS)
-#define TXQ_TO_COS(txq_index)	((txq_index) / MAX_TXQS_PER_COS)
-
-/* rules for calculating the cids of tx-only connections */
-#define CID_TO_FP(cid)		((cid) % MAX_TXQS_PER_COS)
-#define CID_COS_TO_TX_ONLY_CID(cid, cos)	(cid + cos * MAX_TXQS_PER_COS)
-
-/* fp index inside class of service range */
-#define FP_COS_TO_TXQ(fp, cos)    ((fp)->index + cos * MAX_TXQS_PER_COS)
-
-/*
- * 0..15 eth cos0
- * 16..31 eth cos1 if applicable
- * 32..47 eth cos2 If applicable
- * fcoe queue follows eth queues (16, 32, 48 depending on cos)
- */
-#define MAX_ETH_TXQ_IDX(bp)	(MAX_TXQS_PER_COS * (bp)->max_cos)
-#define FCOE_TXQ_IDX(bp)	(MAX_ETH_TXQ_IDX(bp))
-
-/* fast path */
-struct sw_rx_bd {
-	struct sk_buff	*skb;
-	DEFINE_DMA_UNMAP_ADDR(mapping);
-};
-
-struct sw_tx_bd {
-	struct sk_buff	*skb;
-	u16		first_bd;
-	u8		flags;
-/* Set on the first BD descriptor when there is a split BD */
-#define BNX2X_TSO_SPLIT_BD		(1<<0)
-};
-
-struct sw_rx_page {
-	struct page	*page;
-	DEFINE_DMA_UNMAP_ADDR(mapping);
-};
-
-union db_prod {
-	struct doorbell_set_prod data;
-	u32		raw;
-};
-
-
-/* MC hsi */
-#define BCM_PAGE_SHIFT		12
-#define BCM_PAGE_SIZE		(1 << BCM_PAGE_SHIFT)
-#define BCM_PAGE_MASK		(~(BCM_PAGE_SIZE - 1))
-#define BCM_PAGE_ALIGN(addr)	(((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
-
-#define PAGES_PER_SGE_SHIFT	0
-#define PAGES_PER_SGE		(1 << PAGES_PER_SGE_SHIFT)
-#define SGE_PAGE_SIZE		PAGE_SIZE
-#define SGE_PAGE_SHIFT		PAGE_SHIFT
-#define SGE_PAGE_ALIGN(addr)	PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
-
-/* SGE ring related macros */
-#define NUM_RX_SGE_PAGES	2
-#define RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
-#define MAX_RX_SGE_CNT		(RX_SGE_CNT - 2)
-/* RX_SGE_CNT is promised to be a power of 2 */
-#define RX_SGE_MASK		(RX_SGE_CNT - 1)
-#define NUM_RX_SGE		(RX_SGE_CNT * NUM_RX_SGE_PAGES)
-#define MAX_RX_SGE		(NUM_RX_SGE - 1)
-#define NEXT_SGE_IDX(x)		((((x) & RX_SGE_MASK) == \
-				  (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
-#define RX_SGE(x)		((x) & MAX_RX_SGE)
-
-/* Manipulate a bit vector defined as an array of u64 */
-
-/* Number of bits in one sge_mask array element */
-#define BIT_VEC64_ELEM_SZ		64
-#define BIT_VEC64_ELEM_SHIFT		6
-#define BIT_VEC64_ELEM_MASK		((u64)BIT_VEC64_ELEM_SZ - 1)
-
-
-#define __BIT_VEC64_SET_BIT(el, bit) \
-	do { \
-		el = ((el) | ((u64)0x1 << (bit))); \
-	} while (0)
-
-#define __BIT_VEC64_CLEAR_BIT(el, bit) \
-	do { \
-		el = ((el) & (~((u64)0x1 << (bit)))); \
-	} while (0)
-
-
-#define BIT_VEC64_SET_BIT(vec64, idx) \
-	__BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
-			   (idx) & BIT_VEC64_ELEM_MASK)
-
-#define BIT_VEC64_CLEAR_BIT(vec64, idx) \
-	__BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
-			     (idx) & BIT_VEC64_ELEM_MASK)
-
-#define BIT_VEC64_TEST_BIT(vec64, idx) \
-	(((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
-	((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
-
-/* Creates a bitmask of all ones in less significant bits.
-   idx - index of the most significant bit in the created mask */
-#define BIT_VEC64_ONES_MASK(idx) \
-		(((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
-#define BIT_VEC64_ELEM_ONE_MASK	((u64)(~0))
-
-/*******************************************************/
-
-
-
-/* Number of u64 elements in SGE mask array */
-#define RX_SGE_MASK_LEN			((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
-					 BIT_VEC64_ELEM_SZ)
-#define RX_SGE_MASK_LEN_MASK		(RX_SGE_MASK_LEN - 1)
-#define NEXT_SGE_MASK_ELEM(el)		(((el) + 1) & RX_SGE_MASK_LEN_MASK)
-
-union host_hc_status_block {
-	/* pointer to fp status block e1x */
-	struct host_hc_status_block_e1x *e1x_sb;
-	/* pointer to fp status block e2 */
-	struct host_hc_status_block_e2  *e2_sb;
-};
-
-struct bnx2x_agg_info {
-	/*
-	 * First aggregation buffer is an skb, the following - are pages.
-	 * We will preallocate the skbs for each aggregation when
-	 * we open the interface and will replace the BD at the consumer
-	 * with this one when we receive the TPA_START CQE in order to
-	 * keep the Rx BD ring consistent.
-	 */
-	struct sw_rx_bd		first_buf;
-	u8			tpa_state;
-#define BNX2X_TPA_START			1
-#define BNX2X_TPA_STOP			2
-#define BNX2X_TPA_ERROR			3
-	u8			placement_offset;
-	u16			parsing_flags;
-	u16			vlan_tag;
-	u16			len_on_bd;
-};
-
-#define Q_STATS_OFFSET32(stat_name) \
-			(offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
-
-struct bnx2x_fp_txdata {
-
-	struct sw_tx_bd		*tx_buf_ring;
-
-	union eth_tx_bd_types	*tx_desc_ring;
-	dma_addr_t		tx_desc_mapping;
-
-	u32			cid;
-
-	union db_prod		tx_db;
-
-	u16			tx_pkt_prod;
-	u16			tx_pkt_cons;
-	u16			tx_bd_prod;
-	u16			tx_bd_cons;
-
-	unsigned long		tx_pkt;
-
-	__le16			*tx_cons_sb;
-
-	int			txq_index;
-};
-
-struct bnx2x_fastpath {
-	struct bnx2x		*bp; /* parent */
-
-#define BNX2X_NAPI_WEIGHT       128
-	struct napi_struct	napi;
-	union host_hc_status_block	status_blk;
-	/* chip independed shortcuts into sb structure */
-	__le16			*sb_index_values;
-	__le16			*sb_running_index;
-	/* chip independed shortcut into rx_prods_offset memory */
-	u32			ustorm_rx_prods_offset;
-
-	u32			rx_buf_size;
-
-	dma_addr_t		status_blk_mapping;
-
-	u8			max_cos; /* actual number of active tx coses */
-	struct bnx2x_fp_txdata	txdata[BNX2X_MULTI_TX_COS];
-
-	struct sw_rx_bd		*rx_buf_ring;	/* BDs mappings ring */
-	struct sw_rx_page	*rx_page_ring;	/* SGE pages mappings ring */
-
-	struct eth_rx_bd	*rx_desc_ring;
-	dma_addr_t		rx_desc_mapping;
-
-	union eth_rx_cqe	*rx_comp_ring;
-	dma_addr_t		rx_comp_mapping;
-
-	/* SGE ring */
-	struct eth_rx_sge	*rx_sge_ring;
-	dma_addr_t		rx_sge_mapping;
-
-	u64			sge_mask[RX_SGE_MASK_LEN];
-
-	u32			cid;
-
-	__le16			fp_hc_idx;
-
-	u8			index;		/* number in fp array */
-	u8			cl_id;		/* eth client id */
-	u8			cl_qzone_id;
-	u8			fw_sb_id;	/* status block number in FW */
-	u8			igu_sb_id;	/* status block number in HW */
-
-	u16			rx_bd_prod;
-	u16			rx_bd_cons;
-	u16			rx_comp_prod;
-	u16			rx_comp_cons;
-	u16			rx_sge_prod;
-	/* The last maximal completed SGE */
-	u16			last_max_sge;
-	__le16			*rx_cons_sb;
-	unsigned long		rx_pkt,
-				rx_calls;
-
-	/* TPA related */
-	struct bnx2x_agg_info	tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
-	u8			disable_tpa;
-#ifdef BNX2X_STOP_ON_ERROR
-	u64			tpa_queue_used;
-#endif
-
-	struct tstorm_per_queue_stats old_tclient;
-	struct ustorm_per_queue_stats old_uclient;
-	struct xstorm_per_queue_stats old_xclient;
-	struct bnx2x_eth_q_stats eth_q_stats;
-
-	/* The size is calculated using the following:
-	     sizeof name field from netdev structure +
-	     4 ('-Xx-' string) +
-	     4 (for the digits and to make it DWORD aligned) */
-#define FP_NAME_SIZE		(sizeof(((struct net_device *)0)->name) + 8)
-	char			name[FP_NAME_SIZE];
-
-	/* MACs object */
-	struct bnx2x_vlan_mac_obj mac_obj;
-
-	/* Queue State object */
-	struct bnx2x_queue_sp_obj q_obj;
-
-};
-
-#define bnx2x_fp(bp, nr, var)		(bp->fp[nr].var)
-
-/* Use 2500 as a mini-jumbo MTU for FCoE */
-#define BNX2X_FCOE_MINI_JUMBO_MTU	2500
-
-/* FCoE L2 `fastpath' entry is right after the eth entries */
-#define FCOE_IDX			BNX2X_NUM_ETH_QUEUES(bp)
-#define bnx2x_fcoe_fp(bp)		(&bp->fp[FCOE_IDX])
-#define bnx2x_fcoe(bp, var)		(bnx2x_fcoe_fp(bp)->var)
-#define bnx2x_fcoe_tx(bp, var)		(bnx2x_fcoe_fp(bp)-> \
-						txdata[FIRST_TX_COS_INDEX].var)
-
-
-#define IS_ETH_FP(fp)			(fp->index < \
-					 BNX2X_NUM_ETH_QUEUES(fp->bp))
-#ifdef BCM_CNIC
-#define IS_FCOE_FP(fp)			(fp->index == FCOE_IDX)
-#define IS_FCOE_IDX(idx)		((idx) == FCOE_IDX)
-#else
-#define IS_FCOE_FP(fp)		false
-#define IS_FCOE_IDX(idx)	false
-#endif
-
-
-/* MC hsi */
-#define MAX_FETCH_BD		13	/* HW max BDs per packet */
-#define RX_COPY_THRESH		92
-
-#define NUM_TX_RINGS		16
-#define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
-#define MAX_TX_DESC_CNT		(TX_DESC_CNT - 1)
-#define NUM_TX_BD		(TX_DESC_CNT * NUM_TX_RINGS)
-#define MAX_TX_BD		(NUM_TX_BD - 1)
-#define MAX_TX_AVAIL		(MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
-#define NEXT_TX_IDX(x)		((((x) & MAX_TX_DESC_CNT) == \
-				  (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define TX_BD(x)		((x) & MAX_TX_BD)
-#define TX_BD_POFF(x)		((x) & MAX_TX_DESC_CNT)
-
-/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
-#define NUM_RX_RINGS		8
-#define RX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
-#define MAX_RX_DESC_CNT		(RX_DESC_CNT - 2)
-#define RX_DESC_MASK		(RX_DESC_CNT - 1)
-#define NUM_RX_BD		(RX_DESC_CNT * NUM_RX_RINGS)
-#define MAX_RX_BD		(NUM_RX_BD - 1)
-#define MAX_RX_AVAIL		(MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
-#define MIN_RX_AVAIL		128
-
-#define MIN_RX_SIZE_TPA_HW	(CHIP_IS_E1(bp) ? \
-					ETH_MIN_RX_CQES_WITH_TPA_E1 : \
-					ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
-#define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
-#define MIN_RX_SIZE_TPA		(max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
-#define MIN_RX_SIZE_NONTPA	(max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
-								MIN_RX_AVAIL))
-
-#define NEXT_RX_IDX(x)		((((x) & RX_DESC_MASK) == \
-				  (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
-#define RX_BD(x)		((x) & MAX_RX_BD)
-
-/*
- * As long as CQE is X times bigger than BD entry we have to allocate X times
- * more pages for CQ ring in order to keep it balanced with BD ring
- */
-#define CQE_BD_REL	(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
-#define NUM_RCQ_RINGS		(NUM_RX_RINGS * CQE_BD_REL)
-#define RCQ_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
-#define MAX_RCQ_DESC_CNT	(RCQ_DESC_CNT - 1)
-#define NUM_RCQ_BD		(RCQ_DESC_CNT * NUM_RCQ_RINGS)
-#define MAX_RCQ_BD		(NUM_RCQ_BD - 1)
-#define MAX_RCQ_AVAIL		(MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
-#define NEXT_RCQ_IDX(x)		((((x) & MAX_RCQ_DESC_CNT) == \
-				  (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define RCQ_BD(x)		((x) & MAX_RCQ_BD)
-
-
-/* This is needed for determining of last_max */
-#define SUB_S16(a, b)		(s16)((s16)(a) - (s16)(b))
-#define SUB_S32(a, b)		(s32)((s32)(a) - (s32)(b))
-
-
-#define BNX2X_SWCID_SHIFT	17
-#define BNX2X_SWCID_MASK	((0x1 << BNX2X_SWCID_SHIFT) - 1)
-
-/* used on a CID received from the HW */
-#define SW_CID(x)			(le32_to_cpu(x) & BNX2X_SWCID_MASK)
-#define CQE_CMD(x)			(le32_to_cpu(x) >> \
-					COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
-
-#define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr_hi), \
-						 le32_to_cpu((bd)->addr_lo))
-#define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))
-
-#define BNX2X_DB_MIN_SHIFT		3	/* 8 bytes */
-#define BNX2X_DB_SHIFT			7	/* 128 bytes*/
-#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
-#error "Min DB doorbell stride is 8"
-#endif
-#define DPM_TRIGER_TYPE			0x40
-#define DOORBELL(bp, cid, val) \
-	do { \
-		writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
-		       DPM_TRIGER_TYPE); \
-	} while (0)
-
-
-/* TX CSUM helpers */
-#define SKB_CS_OFF(skb)		(offsetof(struct tcphdr, check) - \
-				 skb->csum_offset)
-#define SKB_CS(skb)		(*(u16 *)(skb_transport_header(skb) + \
-					  skb->csum_offset))
-
-#define pbd_tcp_flags(skb)	(ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
-
-#define XMIT_PLAIN			0
-#define XMIT_CSUM_V4			0x1
-#define XMIT_CSUM_V6			0x2
-#define XMIT_CSUM_TCP			0x4
-#define XMIT_GSO_V4			0x8
-#define XMIT_GSO_V6			0x10
-
-#define XMIT_CSUM			(XMIT_CSUM_V4 | XMIT_CSUM_V6)
-#define XMIT_GSO			(XMIT_GSO_V4 | XMIT_GSO_V6)
-
-
-/* stuff added to make the code fit 80Col */
-#define CQE_TYPE(cqe_fp_flags)	 ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
-#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
-#define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
-#define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
-#define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
-
-#define ETH_RX_ERROR_FALGS		ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
-
-#define BNX2X_IP_CSUM_ERR(cqe) \
-			(!((cqe)->fast_path_cqe.status_flags & \
-			   ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
-			 ((cqe)->fast_path_cqe.type_error_flags & \
-			  ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
-
-#define BNX2X_L4_CSUM_ERR(cqe) \
-			(!((cqe)->fast_path_cqe.status_flags & \
-			   ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
-			 ((cqe)->fast_path_cqe.type_error_flags & \
-			  ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
-
-#define BNX2X_RX_CSUM_OK(cqe) \
-			(!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
-
-#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
-				(((le16_to_cpu(flags) & \
-				   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
-				  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
-				 == PRS_FLAG_OVERETH_IPV4)
-#define BNX2X_RX_SUM_FIX(cqe) \
-	BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
-
-
-#define FP_USB_FUNC_OFF	\
-			offsetof(struct cstorm_status_block_u, func)
-#define FP_CSB_FUNC_OFF	\
-			offsetof(struct cstorm_status_block_c, func)
-
-#define HC_INDEX_TOE_RX_CQ_CONS		0 /* Formerly Ustorm TOE CQ index */
-					  /* (HC_INDEX_U_TOE_RX_CQ_CONS)  */
-#define HC_INDEX_ETH_RX_CQ_CONS		1 /* Formerly Ustorm ETH CQ index */
-					  /* (HC_INDEX_U_ETH_RX_CQ_CONS)  */
-#define HC_INDEX_ETH_RX_BD_CONS		2 /* Formerly Ustorm ETH BD index */
-					  /* (HC_INDEX_U_ETH_RX_BD_CONS)  */
-
-#define HC_INDEX_TOE_TX_CQ_CONS		4 /* Formerly Cstorm TOE CQ index   */
-					  /* (HC_INDEX_C_TOE_TX_CQ_CONS)    */
-#define HC_INDEX_ETH_TX_CQ_CONS_COS0	5 /* Formerly Cstorm ETH CQ index   */
-					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */
-#define HC_INDEX_ETH_TX_CQ_CONS_COS1	6 /* Formerly Cstorm ETH CQ index   */
-					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */
-#define HC_INDEX_ETH_TX_CQ_CONS_COS2	7 /* Formerly Cstorm ETH CQ index   */
-					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */
-
-#define HC_INDEX_ETH_FIRST_TX_CQ_CONS	HC_INDEX_ETH_TX_CQ_CONS_COS0
-
-
-#define BNX2X_RX_SB_INDEX \
-	(&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
-
-#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
-
-#define BNX2X_TX_SB_INDEX_COS0 \
-	(&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
-
-/* end of fast path */
-
-/* common */
-
-struct bnx2x_common {
-
-	u32			chip_id;
-/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
-#define CHIP_ID(bp)			(bp->common.chip_id & 0xfffffff0)
-
-#define CHIP_NUM(bp)			(bp->common.chip_id >> 16)
-#define CHIP_NUM_57710			0x164e
-#define CHIP_NUM_57711			0x164f
-#define CHIP_NUM_57711E			0x1650
-#define CHIP_NUM_57712			0x1662
-#define CHIP_NUM_57712_MF		0x1663
-#define CHIP_NUM_57713			0x1651
-#define CHIP_NUM_57713E			0x1652
-#define CHIP_NUM_57800			0x168a
-#define CHIP_NUM_57800_MF		0x16a5
-#define CHIP_NUM_57810			0x168e
-#define CHIP_NUM_57810_MF		0x16ae
-#define CHIP_NUM_57840			0x168d
-#define CHIP_NUM_57840_MF		0x16ab
-#define CHIP_IS_E1(bp)			(CHIP_NUM(bp) == CHIP_NUM_57710)
-#define CHIP_IS_57711(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711)
-#define CHIP_IS_57711E(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711E)
-#define CHIP_IS_57712(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712)
-#define CHIP_IS_57712_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712_MF)
-#define CHIP_IS_57800(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800)
-#define CHIP_IS_57800_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800_MF)
-#define CHIP_IS_57810(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810)
-#define CHIP_IS_57810_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810_MF)
-#define CHIP_IS_57840(bp)		(CHIP_NUM(bp) == CHIP_NUM_57840)
-#define CHIP_IS_57840_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57840_MF)
-#define CHIP_IS_E1H(bp)			(CHIP_IS_57711(bp) || \
-					 CHIP_IS_57711E(bp))
-#define CHIP_IS_E2(bp)			(CHIP_IS_57712(bp) || \
-					 CHIP_IS_57712_MF(bp))
-#define CHIP_IS_E3(bp)			(CHIP_IS_57800(bp) || \
-					 CHIP_IS_57800_MF(bp) || \
-					 CHIP_IS_57810(bp) || \
-					 CHIP_IS_57810_MF(bp) || \
-					 CHIP_IS_57840(bp) || \
-					 CHIP_IS_57840_MF(bp))
-#define CHIP_IS_E1x(bp)			(CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
-#define USES_WARPCORE(bp)		(CHIP_IS_E3(bp))
-#define IS_E1H_OFFSET			(!CHIP_IS_E1(bp))
-
-#define CHIP_REV_SHIFT			12
-#define CHIP_REV_MASK			(0xF << CHIP_REV_SHIFT)
-#define CHIP_REV_VAL(bp)		(bp->common.chip_id & CHIP_REV_MASK)
-#define CHIP_REV_Ax			(0x0 << CHIP_REV_SHIFT)
-#define CHIP_REV_Bx			(0x1 << CHIP_REV_SHIFT)
-/* assume maximum 5 revisions */
-#define CHIP_REV_IS_SLOW(bp)		(CHIP_REV_VAL(bp) > 0x00005000)
-/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
-#define CHIP_REV_IS_EMUL(bp)		((CHIP_REV_IS_SLOW(bp)) && \
-					 !(CHIP_REV_VAL(bp) & 0x00001000))
-/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
-#define CHIP_REV_IS_FPGA(bp)		((CHIP_REV_IS_SLOW(bp)) && \
-					 (CHIP_REV_VAL(bp) & 0x00001000))
-
-#define CHIP_TIME(bp)			((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
-					((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
-
-#define CHIP_METAL(bp)			(bp->common.chip_id & 0x00000ff0)
-#define CHIP_BOND_ID(bp)		(bp->common.chip_id & 0x0000000f)
-#define CHIP_REV_SIM(bp)		(((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
-					   (CHIP_REV_SHIFT + 1)) \
-						<< CHIP_REV_SHIFT)
-#define CHIP_REV(bp)			(CHIP_REV_IS_SLOW(bp) ? \
-						CHIP_REV_SIM(bp) :\
-						CHIP_REV_VAL(bp))
-#define CHIP_IS_E3B0(bp)		(CHIP_IS_E3(bp) && \
-					 (CHIP_REV(bp) == CHIP_REV_Bx))
-#define CHIP_IS_E3A0(bp)		(CHIP_IS_E3(bp) && \
-					 (CHIP_REV(bp) == CHIP_REV_Ax))
-
-	int			flash_size;
-#define BNX2X_NVRAM_1MB_SIZE			0x20000	/* 1M bit in bytes */
-#define BNX2X_NVRAM_TIMEOUT_COUNT		30000
-#define BNX2X_NVRAM_PAGE_SIZE			256
-
-	u32			shmem_base;
-	u32			shmem2_base;
-	u32			mf_cfg_base;
-	u32			mf2_cfg_base;
-
-	u32			hw_config;
-
-	u32			bc_ver;
-
-	u8			int_block;
-#define INT_BLOCK_HC			0
-#define INT_BLOCK_IGU			1
-#define INT_BLOCK_MODE_NORMAL		0
-#define INT_BLOCK_MODE_BW_COMP		2
-#define CHIP_INT_MODE_IS_NBC(bp)		\
-			(!CHIP_IS_E1x(bp) &&	\
-			!((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
-#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
-
-	u8			chip_port_mode;
-#define CHIP_4_PORT_MODE			0x0
-#define CHIP_2_PORT_MODE			0x1
-#define CHIP_PORT_MODE_NONE			0x2
-#define CHIP_MODE(bp)			(bp->common.chip_port_mode)
-#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
-};
-
-/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
-#define BNX2X_IGU_STAS_MSG_VF_CNT 64
-#define BNX2X_IGU_STAS_MSG_PF_CNT 4
-
-/* end of common */
-
-/* port */
-
-struct bnx2x_port {
-	u32			pmf;
-
-	u32			link_config[LINK_CONFIG_SIZE];
-
-	u32			supported[LINK_CONFIG_SIZE];
-/* link settings - missing defines */
-#define SUPPORTED_2500baseX_Full	(1 << 15)
-
-	u32			advertising[LINK_CONFIG_SIZE];
-/* link settings - missing defines */
-#define ADVERTISED_2500baseX_Full	(1 << 15)
-
-	u32			phy_addr;
-
-	/* used to synchronize phy accesses */
-	struct mutex		phy_mutex;
-	int			need_hw_lock;
-
-	u32			port_stx;
-
-	struct nig_stats	old_nig_stats;
-};
-
-/* end of port */
-
-#define STATS_OFFSET32(stat_name) \
-			(offsetof(struct bnx2x_eth_stats, stat_name) / 4)
-
-/* slow path */
-
-/* slow path work-queue */
-extern struct workqueue_struct *bnx2x_wq;
-
-#define BNX2X_MAX_NUM_OF_VFS	64
-#define BNX2X_VF_ID_INVALID	0xFF
-
-/*
- * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
- * control by the number of fast-path status blocks supported by the
- * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
- * status block represents an independent interrupts context that can
- * serve a regular L2 networking queue. However special L2 queues such
- * as the FCoE queue do not require a FP-SB and other components like
- * the CNIC may consume FP-SB reducing the number of possible L2 queues
- *
- * If the maximum number of FP-SB available is X then:
- * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
- *    regular L2 queues is Y=X-1
- * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
- * c. If the FCoE L2 queue is supported the actual number of L2 queues
- *    is Y+1
- * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
- *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
- *    FP interrupt context for the CNIC).
- * e. The number of HW context (CID count) is always X or X+1 if FCoE
- *    L2 queue is supported. the cid for the FCoE L2 queue is always X.
- */
-
-/* fast-path interrupt contexts E1x */
-#define FP_SB_MAX_E1x		16
-/* fast-path interrupt contexts E2 */
-#define FP_SB_MAX_E2		HC_SB_MAX_SB_E2
-
-union cdu_context {
-	struct eth_context eth;