diff options
| author | Mike Dunn <mikedunn@newsguy.com> | 2012-03-11 14:21:11 -0700 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-03-27 00:56:46 +0100 |
| commit | 6a918bade9dab40aaef80559bd1169c69e8d69cb (patch) | |
| tree | 1be69789f9b6c6e064a36f4ef6e142a8ec0058b5 /drivers/mtd/nand/pxa3xx_nand.c | |
| parent | 1d0b95b0834087ba3653f69c24483d63a26d51a7 (diff) | |
mtd: flash drivers set ecc strength
Flash device drivers initialize 'ecc_strength' in struct mtd_info, which is the
maximum number of bit errors that can be corrected in one writesize region.
Drivers using the nand interface intitialize 'strength' in struct nand_ecc_ctrl,
which is the maximum number of bit errors that can be corrected in one ecc step.
Nand infrastructure code translates this to 'ecc_strength'.
Also for nand drivers, the nand infrastructure code sets ecc.strength for ecc
modes NAND_ECC_SOFT, NAND_ECC_SOFT_BCH, and NAND_ECC_NONE. It is set in the
driver for all other modes.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/pxa3xx_nand.c')
| -rw-r--r-- | drivers/mtd/nand/pxa3xx_nand.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index d3bdc909c93..def50caa6f8 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1002,6 +1002,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) KEEP_CONFIG: chip->ecc.mode = NAND_ECC_HW; chip->ecc.size = host->page_size; + chip->ecc.strength = 1; chip->options = NAND_NO_AUTOINCR; chip->options |= NAND_NO_READRDY; |