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authorShawn Guo <shawn.guo@linaro.org>2012-04-11 13:29:31 +0800
committerVinod Koul <vinod.koul@linux.intel.com>2012-04-20 15:35:58 +0530
commitd04525ed0323709711277563a2c76e446a017423 (patch)
tree76766ed95d698f3ec98762301e42f703e774381c /drivers/mmc
parent60f2951e3ad9b833bc12e2ea7652be2611771792 (diff)
dma: mxs-dma: enable channel in device_issue_pending call
Enable channel in device_issue_pending call, so that the order between cookie assignment and channel enabling can be ensured naturally. It fixes the mxs gpmi-nand breakage which is caused by the incorrect order of cookie assigning and channel enabling. Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Huang Shijie <b32955@freescale.com> Tested-by <samgandhi9@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mxs-mmc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index b0f2ef98818..e3f5af96ab8 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -363,6 +363,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
goto out;
dmaengine_submit(desc);
+ dma_async_issue_pending(host->dmach);
return;
out:
@@ -403,6 +404,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
goto out;
dmaengine_submit(desc);
+ dma_async_issue_pending(host->dmach);
return;
out:
@@ -531,6 +533,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
goto out;
dmaengine_submit(desc);
+ dma_async_issue_pending(host->dmach);
return;
out:
dev_warn(mmc_dev(host->mmc),