V4L/DVB(7872): mxl5005s: checkpatch.pl compliance

4 exceptions where the code would read very ugly otherwise.

Signed-off-by: Steven Toth <stoth@hauppauge.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>

2 files changed, 1029 insertions, 1471 deletions

diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 45ac6a9e71a..21dca5bdca7 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -86,34 +86,30 @@ static int debug = 2;
 #define MASTER_CONTROL_ADDR     9
 
 /* Enumeration of Master Control Register State */
-typedef enum
-{
+enum master_control_state {
 	MC_LOAD_START = 1,
 	MC_POWER_DOWN,
 	MC_SYNTH_RESET,
 	MC_SEQ_OFF
-} Master_Control_State;
+};
 
 /* Enumeration of MXL5005 Tuner Modulation Type */
-typedef enum
-{
+enum {
 	MXL_DEFAULT_MODULATION = 0,
 	MXL_DVBT,
 	MXL_ATSC,
 	MXL_QAM,
 	MXL_ANALOG_CABLE,
 	MXL_ANALOG_OTA
-} Tuner_Modu_Type;
+} tuner_modu_type;
 
 /* MXL5005 Tuner Register Struct */
-typedef struct _TunerReg_struct
-{
+struct TunerReg {
 	u16 Reg_Num;	/* Tuner Register Address */
-	u16 Reg_Val;	/* Current sofware programmed value waiting to be writen */
-} TunerReg_struct;
+	u16 Reg_Val;	/* Current sw programmed value waiting to be writen */
+};
 
-typedef enum
-{
+enum {
 	/* Initialization Control Names */
 	DN_IQTN_AMP_CUT = 1,       /* 1 */
 	BB_MODE,                   /* 2 */
@@ -219,16 +215,14 @@ typedef enum
 #define MXL5005S_BB_DLPF_BANDSEL_LSB		3
 
 /* Standard modes */
-enum
-{
+enum {
 	MXL5005S_STANDARD_DVBT,
 	MXL5005S_STANDARD_ATSC,
 };
 #define MXL5005S_STANDARD_MODE_NUM		2
 
 /* Bandwidth modes */
-enum
-{
+enum {
 	MXL5005S_BANDWIDTH_6MHZ = 6000000,
 	MXL5005S_BANDWIDTH_7MHZ = 7000000,
 	MXL5005S_BANDWIDTH_8MHZ = 8000000,
@@ -236,17 +230,16 @@ enum
 #define MXL5005S_BANDWIDTH_MODE_NUM		3
 
 /* MXL5005 Tuner Control Struct */
-typedef struct _TunerControl_struct {
+struct TunerControl {
 	u16 Ctrl_Num;	/* Control Number */
 	u16 size;	/* Number of bits to represent Value */
-	u16 addr[25];	/* Array of Tuner Register Address for each bit position */
-	u16 bit[25];	/* Array of bit position in Register Address for each bit position */
+	u16 addr[25];	/* Array of Tuner Register Address for each bit pos */
+	u16 bit[25];	/* Array of bit pos in Reg Addr for each bit pos */
 	u16 val[25];	/* Binary representation of Value */
-} TunerControl_struct;
+};
 
 /* MXL5005 Tuner Struct */
-struct mxl5005s_state
-{
+struct mxl5005s_state {
 	u8	Mode;		/* 0: Analog Mode ; 1: Digital Mode */
 	u8	IF_Mode;	/* for Analog Mode, 0: zero IF; 1: low IF */
 	u32	Chan_Bandwidth;	/* filter  channel bandwidth (6, 7, 8) */
@@ -256,14 +249,18 @@ struct mxl5005s_state
 	u32	Fxtal;		/* XTAL Frequency */
 	u8	AGC_Mode;	/* AGC Mode 0: Dual AGC; 1: Single AGC */
 	u16	TOP;		/* Value: take over point */
-	u8	CLOCK_OUT;	/* 0: turn off clock out; 1: turn on clock out */
+	u8	CLOCK_OUT;	/* 0: turn off clk out; 1: turn on clock out */
 	u8	DIV_OUT;	/* 4MHz or 16MHz */
 	u8	CAPSELECT;	/* 0: disable On-Chip pulling cap; 1: enable */
 	u8	EN_RSSI;	/* 0: disable RSSI; 1: enable RSSI */
-	u8	Mod_Type;	/* Modulation Type; */
-				/* 0 - Default;	1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
-	u8	TF_Type;	/* Tracking Filter Type */
-				/* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
+
+	/* Modulation Type; */
+	/* 0 - Default;	1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
+	u8	Mod_Type;
+
+	/* Tracking Filter Type */
+	/* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
+	u8	TF_Type;
 
 	/* Calculated Settings */
 	u32	RF_LO;		/* Synth RF LO Frequency */
@@ -271,22 +268,22 @@ struct mxl5005s_state
 	u32	TG_LO;		/* Synth TG_LO Frequency */
 
 	/* Pointers to ControlName Arrays */
-	u16	Init_Ctrl_Num;			/* Number of INIT Control Names */
-	TunerControl_struct
-		Init_Ctrl[INITCTRL_NUM];	/* INIT Control Names Array Pointer */
+	u16	Init_Ctrl_Num;		/* Number of INIT Control Names */
+	struct TunerControl
+		Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
 
-	u16	CH_Ctrl_Num;			/* Number of CH Control Names */
-	TunerControl_struct
-		CH_Ctrl[CHCTRL_NUM];		/* CH Control Name Array Pointer */
+	u16	CH_Ctrl_Num;		/* Number of CH Control Names */
+	struct TunerControl
+		CH_Ctrl[CHCTRL_NUM];	/* CH Control Name Array Pointer */
 
-	u16	MXL_Ctrl_Num;			/* Number of MXL Control Names */
-	TunerControl_struct
-		MXL_Ctrl[MXLCTRL_NUM];		/* MXL Control Name Array Pointer */
+	u16	MXL_Ctrl_Num;		/* Number of MXL Control Names */
+	struct TunerControl
+		MXL_Ctrl[MXLCTRL_NUM];	/* MXL Control Name Array Pointer */
 
 	/* Pointer to Tuner Register Array */
-	u16	TunerRegs_Num;			/* Number of Tuner Registers */
-	TunerReg_struct
-		TunerRegs[TUNER_REGS_NUM];	/* Tuner Register Array Pointer */
+	u16	TunerRegs_Num;		/* Number of Tuner Registers */
+	struct TunerReg
+		TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
 
 	/* Linux driver framework specific */
 	struct mxl5005s_config *config;
@@ -302,21 +299,27 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
 u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
 u16 MXL_GetMasterControl(u8 *MasterReg, int state);
 void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
-u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
+u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
+	u8 *RegVal, int *count);
 u32 MXL_Ceiling(u32 value, u32 resolution);
 u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
 u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
-u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup);
+u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
+	u32 value, u16 controlGroup);
 u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
-u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count);
+u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
+	u8 *RegVal, int *count);
 u32 MXL_GetXtalInt(u32 Xtal_Freq);
 u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
 void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
 void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
-u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
-int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len);
+u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
+	u8 *RegVal, int *count);
+int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
+	u8 *datatable, u8 len);
 u16 MXL_IFSynthInit(struct dvb_frontend *fe);
-int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
+int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
+	u32 bandwidth);
 int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
 
 /* ----------------------------------------------------------------
@@ -343,16 +346,16 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
 
 	dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
 
-	// Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
+	/* Set MxL5005S tuner RF frequency according to example code. */
 
-	// Tuner RF frequency setting stage 0
-	MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
+	/* Tuner RF frequency setting stage 0 */
+	MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
 	AddrTable[0] = MASTER_CONTROL_ADDR;
 	ByteTable[0] |= state->config->AgcMasterByte;
 
 	mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
 
-	// Tuner RF frequency setting stage 1
+	/* Tuner RF frequency setting stage 1 */
 	MXL_TuneRF(fe, RfFreqHz);
 
 	MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
@@ -360,26 +363,28 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
 	MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
 	MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
 	MXL_ControlWrite(fe, IF_DIVVAL, 8);
-	MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ;
+	MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
 
-	MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
+	MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 	AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
-	ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte;
+	ByteTable[TableLen] = MasterControlByte |
+		state->config->AgcMasterByte;
 	TableLen += 1;
 
 	mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
 
-	// Wait 30 ms.
+	/* Wait 30 ms. */
 	msleep(150);
 
-	// Tuner RF frequency setting stage 2
-	MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
-	MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ;
-	MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ;
+	/* Tuner RF frequency setting stage 2 */
+	MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
+	MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
+	MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
 
-	MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
+	MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 	AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
-	ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ;
+	ByteTable[TableLen] = MasterControlByte |
+		state->config->AgcMasterByte ;
 	TableLen += 1;
 
 	mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
@@ -398,7 +403,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
 	state->TunerRegs_Num = TUNER_REGS_NUM ;
-//	state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
 
 	state->TunerRegs[0].Reg_Num = 9 ;
 	state->TunerRegs[0].Reg_Val = 0x40 ;
@@ -1655,9 +1659,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe)
 	return 0 ;
 }
 
-// MaxLinear source code - MXL5005_c.cpp
-// MXL5005.cpp : Defines the initialization routines for the DLL.
-// 2.6.12
 void InitTunerControls(struct dvb_frontend *fe)
 {
 	MXL5005_RegisterInit(fe);
@@ -1667,57 +1668,28 @@ void InitTunerControls(struct dvb_frontend *fe)
 #endif
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_ConfigTuner                                           //
-//                                                                           //
-// Description:    Configure MXL5005Tuner structure for desired              //
-//                 Channel Bandwidth/Channel Frequency                       //
-//                                                                           //
-//                                                                           //
-// Functions used:                                                           //
-//                 MXL_SynthIFLO_Calc                                        //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner_struct: structure defined at higher level           //
-//                 Mode:         Tuner Mode (Analog/Digital)                 //
-//                 IF_Mode:      IF Mode ( Zero/Low )                        //
-//		   Bandwidth:    Filter Channel Bandwidth (in Hz)            //
-//                 IF_out:       Desired IF out Frequency (in Hz)            //
-//                 Fxtal:        Crystal Frerquency (in Hz)                  //
-//		   TOP:		 0: Dual AGC; Value: take over point         //
-//		   IF_OUT_LOAD:	 IF out load resistor (200/300 Ohms)	 //
-//		   CLOCK_OUT:	 0: Turn off clock out; 1: turn on clock out //
-//		   DIV_OUT:      0: Div-1; 1: Div-4			 //
-//		   CAPSELECT:	 0: Disable On-chip pulling cap; 1: Enable   //
-//		   EN_RSSI:	 0: Disable RSSI; 1: Enable RSSI	 //
-//                                                                           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
-		u8	Mode,		/* 0: Analog Mode ; 1: Digital Mode */
-		u8	IF_mode,	/* for Analog Mode, 0: zero IF; 1: low IF */
-		u32	Bandwidth,	/* filter  channel bandwidth (6, 7, 8) */
-		u32	IF_out,		/* Desired IF Out Frequency */
-		u32	Fxtal,		/* XTAL Frequency */
-		u8	AGC_Mode,	/* AGC Mode - Dual AGC: 0, Single AGC: 1 */
-		u16	TOP,		/* 0: Dual AGC; Value: take over point */
-		u16	IF_OUT_LOAD,	/* IF Out Load Resistor (200 / 300 Ohms) */
-		u8	CLOCK_OUT, 	/* 0: turn off clock out; 1: turn on clock out */
-		u8	DIV_OUT,	/* 0: Div-1; 1: Div-4 */
-		u8	CAPSELECT, 	/* 0: disable On-Chip pulling cap; 1: enable */
-		u8	EN_RSSI, 	/* 0: disable RSSI; 1: enable RSSI */
-		u8	Mod_Type,	/* Modulation Type; */
-					/* 0 - Default;	1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
-		u8	TF_Type		/* Tracking Filter */
-					/* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
-		)
+	u8	Mode,		/* 0: Analog Mode ; 1: Digital Mode */
+	u8	IF_mode,	/* for Analog Mode, 0: zero IF; 1: low IF */
+	u32	Bandwidth,	/* filter  channel bandwidth (6, 7, 8) */
+	u32	IF_out,		/* Desired IF Out Frequency */
+	u32	Fxtal,		/* XTAL Frequency */
+	u8	AGC_Mode,	/* AGC Mode - Dual AGC: 0, Single AGC: 1 */
+	u16	TOP,		/* 0: Dual AGC; Value: take over point */
+	u16	IF_OUT_LOAD,	/* IF Out Load Resistor (200 / 300 Ohms) */
+	u8	CLOCK_OUT, 	/* 0: turn off clk out; 1: turn on clock out */
+	u8	DIV_OUT,	/* 0: Div-1; 1: Div-4 */
+	u8	CAPSELECT, 	/* 0: disable On-Chip pulling cap; 1: enable */
+	u8	EN_RSSI, 	/* 0: disable RSSI; 1: enable RSSI */
+
+	/* Modulation Type; */
+	/* 0 - Default;	1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
+	u8	Mod_Type,
+
+	/* Tracking Filter */
+	/* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
+	u8	TF_Type
+	)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
 	u16 status = 0;
@@ -1746,105 +1718,40 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
 	return status;
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_SynthIFLO_Calc                                        //
-//                                                                           //
-// Description:    Calculate Internal IF-LO Frequency                        //
-//                                                                           //
-// Globals:                                                                  //
-//                 NONE                                                      //
-//                                                                           //
-// Functions used:                                                           //
-//                 NONE                                                      //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner_struct: structure defined at higher level           //
-//                                                                           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
 	if (state->Mode == 1) /* Digital Mode */
 		state->IF_LO = state->IF_OUT;
-	else /* Analog Mode */
-	{
-		if(state->IF_Mode == 0) /* Analog Zero IF mode */
+	else /* Analog Mode */ {
+		if (state->IF_Mode == 0) /* Analog Zero IF mode */
 			state->IF_LO = state->IF_OUT + 400000;
 		else /* Analog Low IF mode */
 			state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
 	}
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_SynthRFTGLO_Calc                                      //
-//                                                                           //
-// Description:    Calculate Internal RF-LO frequency and                    //
-//                 internal Tone-Gen(TG)-LO frequency                        //
-//                                                                           //
-// Globals:                                                                  //
-//                 NONE                                                      //
-//                                                                           //
-// Functions used:                                                           //
-//                 NONE                                                      //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner_struct: structure defined at higher level           //
-//                                                                           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
 
 	if (state->Mode == 1) /* Digital Mode */ {
-			//remove 20.48MHz setting for 2.6.10
+			/* remove 20.48MHz setting for 2.6.10 */
 			state->RF_LO = state->RF_IN;
-			state->TG_LO = state->RF_IN - 750000;  //change for 2.6.6
+			/* change for 2.6.6 */
+			state->TG_LO = state->RF_IN - 750000;
 	} else /* Analog Mode */ {
-		if(state->IF_Mode == 0) /* Analog Zero IF mode */ {
+		if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
 			state->RF_LO = state->RF_IN - 400000;
 			state->TG_LO = state->RF_IN - 1750000;
 		} else /* Analog Low IF mode */ {
 			state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
-			state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000;
+			state->TG_LO = state->RF_IN -
+				state->Chan_Bandwidth + 500000;
 		}
 	}
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_OverwriteICDefault                                    //
-//                                                                           //
-// Description:    Overwrite the Default Register Setting                    //
-//                                                                           //
-//                                                                           //
-// Functions used:                                                           //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner_struct: structure defined at higher level           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
 {
 	u16 status = 0;
@@ -1857,31 +1764,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
 	return status;
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_BlockInit                                             //
-//                                                                           //
-// Description:    Tuner Initialization as a function of 'User Settings'     //
-//                  * User settings in Tuner strcuture must be assigned      //
-//                    first                                                  //
-//                                                                           //
-// Globals:                                                                  //
-//                 NONE                                                      //
-//                                                                           //
-// Functions used:                                                           //
-//                 Tuner_struct: structure defined at higher level           //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner       : Tuner structure defined at higher level     //
-//                                                                           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 u16 MXL_BlockInit(struct dvb_frontend *fe)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
@@ -1902,42 +1784,45 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 	/* Initialize Low-Pass Filter */
 	if (state->Mode) { /* Digital Mode */
 		switch (state->Chan_Bandwidth) {
-			case 8000000:
-				status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
-				break;
-			case 7000000:
-				status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
-				break;
-			case 6000000:
-				printk("%s() doing 6MHz digital\n", __func__);
-				status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
-				break;
+		case 8000000:
+			status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
+			break;
+		case 7000000:
+			status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
+			break;
+		case 6000000:
+			status += MXL_ControlWrite(fe,
+					BB_DLPF_BANDSEL, 3);
+			break;
 		}
 	} else { /* Analog Mode */
 		switch (state->Chan_Bandwidth) {
-			case 8000000:	/* Low Zero */
-				status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3));
-				break;
-			case 7000000:
-				status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4));
-				break;
-			case 6000000:
-				status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5));
-				break;
+		case 8000000:	/* Low Zero */
+			status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
+					(state->IF_Mode ? 0 : 3));
+			break;
+		case 7000000:
+			status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
+					(state->IF_Mode ? 1 : 4));
+			break;
+		case 6000000:
+			status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
+					(state->IF_Mode ? 2 : 5));
+			break;
 		}
 	}
 
 	/* Charge Pump Control Dig  Ana */
-	status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,      state->Mode ? 5 : 8);
-	status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
+	status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
+	status += MXL_ControlWrite(fe,
+		RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
 	status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
 
 	/* AGC TOP Control */
 	if (state->AGC_Mode == 0) /* Dual AGC */ {
 		status += MXL_ControlWrite(fe, AGC_IF, 15);
 		status += MXL_ControlWrite(fe, AGC_RF, 15);
-	}
-	else /*  Single AGC Mode Dig  Ana */
+	} else /*  Single AGC Mode Dig  Ana */
 		status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
 
 	if (state->TOP == 55) /* TOP == 5.5 */
@@ -2008,7 +1893,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 			status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
 			status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
 		}
-		if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) {
+		if ((state->IF_OUT == 36125000UL) ||
+			(state->IF_OUT == 36150000UL)) {
 			status += MXL_ControlWrite(fe, EN_AAF, 1);
 			status += MXL_ControlWrite(fe, EN_3P, 1);
 			status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
@@ -2021,15 +1907,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 			status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
 		}
 	} else { /* Analog Mode */
-		if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL)
-		{
+		if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
 			status += MXL_ControlWrite(fe, EN_AAF, 1);
 			status += MXL_ControlWrite(fe, EN_3P, 1);
 			status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
 			status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
 		}
-		if (state->IF_OUT > 5000000UL)
-		{
+		if (state->IF_OUT > 5000000UL) {
 			status += MXL_ControlWrite(fe, EN_AAF, 0);
 			status += MXL_ControlWrite(fe, EN_3P, 0);
 			status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
@@ -2073,13 +1957,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 	/* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
 
 	/* Set TG_R_DIV */
-	status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000));
+	status += MXL_ControlWrite(fe, TG_R_DIV,
+		MXL_Ceiling(state->Fxtal, 1000000));
 
 	/* Apply Default value to BB_INITSTATE_DLPF_TUNE */
 
 	/* RSSI Control */
-	if (state->EN_RSSI)
-	{
+	if (state->EN_RSSI) {
 		status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
 		status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
 		status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
@@ -2098,8 +1982,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 	/* Modulation type bit settings
 	 * Override the control values preset
 	 */
-	if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */
-	{
+	if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
 		state->AGC_Mode = 1; /* Single AGC Mode */
 
 		/* Enable RSSI */
@@ -2122,8 +2005,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 			status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
 
 	}
-	if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */
-	{
+	if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
 		state->AGC_Mode = 1;	/* Single AGC Mode */
 
 		/* Enable RSSI */
@@ -2141,14 +2023,15 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 		status += MXL_ControlWrite(fe, RFA_FLR, 2);
 		status += MXL_ControlWrite(fe, RFA_CEIL, 13);
 		status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
-		status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */
+		/* Low Zero */
+		status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
+
 		if (state->IF_OUT <= 6280000UL)	/* Low IF */
 			status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
 		else /* High IF */
 			status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
 	}
-	if (state->Mod_Type == MXL_QAM) /* QAM Mode */
-	{
+	if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
 		state->Mode = MXL_DIGITAL_MODE;
 
 		/* state->AGC_Mode = 1; */ /* Single AGC Mode */
@@ -2163,7 +2046,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 		status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
 		status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
 		status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
-		status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);	/* change here for v2.6.5 */
+		/* change here for v2.6.5 */
+		status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
 
 		if (state->IF_OUT <= 6280000UL)	/* Low IF */
 			status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
@@ -2183,7 +2067,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 		status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
 		status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
 		status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
-		status += MXL_ControlWrite(fe, AGC_IF, 1);  /* change for 2.6.3 */
+		/* change for 2.6.3 */
+		status += MXL_ControlWrite(fe, AGC_IF, 1);
 		status += MXL_ControlWrite(fe, AGC_RF, 15);
 		status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
 	}
@@ -2207,7 +2092,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 	}
 
 	/* RSSI disable */
-	if(state->EN_RSSI == 0) {
+	if (state->EN_RSSI == 0) {
 		status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
 		status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
 		status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
@@ -2217,34 +2102,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
 	return status;
 }
 
-///////////////////////////////////////////////////////////////////////////////
-//                                                                           //
-// Function:       MXL_IFSynthInit                                           //
-//                                                                           //
-// Description:    Tuner IF Synthesizer related register initialization      //
-//                                                                           //
-// Globals:                                                                  //
-//                 NONE                                                      //
-//                                                                           //
-// Functions used:                                                           //
-//                 Tuner_struct: structure defined at higher level           //
-//                                                                           //
-// Inputs:                                                                   //
-//                 Tuner       : Tuner structure defined at higher level     //
-//                                                                           //
-// Outputs:                                                                  //
-//                 Tuner                                                     //
-//                                                                           //
-// Return:                                                                   //
-//                 0 : Successful                                            //
-//               > 0 : Failed                                                //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
 u16 MXL_IFSynthInit(struct dvb_frontend *fe)
 {
 	struct mxl5005s_state *state = fe->tuner_priv;
 	u16 status = 0 ;
-	// Declare Local Variables
 	u32	Fref = 0 ;
 	u32	Kdbl, intModVal ;
 	u32	fracModVal ;
@@ -2255,268 +2116,207 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe)
 	if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
 		Kdbl = 1 ;
 
-	//
-	// IF Synthesizer Control
-	//
-	if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
-	{
+	/* IF Synthesizer Control */
+	if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
 		if (state->IF_LO == 41000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 328000000UL ;
 		}
 		if (state->IF_LO == 47000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 376000000UL ;
 		}
 		if (state->IF_LO == 54000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 324000000UL ;
 		}
 		if (state->IF_LO == 60000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 360000000UL ;
 		}
 		if (state->IF_LO == 39250000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 314000000UL ;
 		}
 		if (state->IF_LO == 39650000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 317200000UL ;
 		}
 		if (state->IF_LO == 40150000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 321200000UL ;
 		}
 		if (state->IF_LO == 40650000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
 			Fref = 325200000UL ;
 		}
 	}
 
-	if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0))
-	{
+	if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
 		if (state->IF_LO == 57000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 342000000UL ;
 		}
 		if (state->IF_LO == 44000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 352000000UL ;
 		}
 		if (state->IF_LO == 43750000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 350000000UL ;
 		}
 		if (state->IF_LO == 36650000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 366500000UL ;
 		}
 		if (state->IF_LO == 36150000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 361500000UL ;
 		}
 		if (state->IF_LO == 36000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 360000000UL ;
 		}
 		if (state->IF_LO == 35250000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 352500000UL ;
 		}
 		if (state->IF_LO == 34750000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 347500000UL ;
 		}
 		if (state->IF_LO == 6280000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 376800000UL ;
 		}
 		if (state->IF_LO == 5000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 360000000UL ;
 		}
 		if (state->IF_LO == 4500000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 360000000UL ;
 		}
 		if (state->IF_LO == 4570000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 365600000UL ;
 		}
 		if (state->IF_LO == 4000000UL) {
-			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05) ;
-			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
+			status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05);
+			status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
 			Fref = 360000000UL ;