[media] drxd: Run lindent across sources

Take a first cleanup pass over the sources to bring them closer to the
Linux coding style.

Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

5 files changed, 1819 insertions, 3675 deletions

diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
index b21c85315d7..d3d6c924653 100644
--- a/drivers/media/dvb/frontends/drxd.h
+++ b/drivers/media/dvb/frontends/drxd.h
@@ -27,8 +27,7 @@
 #include <linux/types.h>
 #include <linux/i2c.h>
 
-struct drxd_config
-{
+struct drxd_config {
 	u8 index;
 
 	u8 pll_address;
@@ -49,9 +48,9 @@ struct drxd_config
 	u8 disable_i2c_gate_ctrl;
 
 	u32 IF;
-	int (*pll_set)       (void *priv, void *priv_params,
-			      u8 pll_addr, u8 demoda_addr, s32 *off);
-	s16 (*osc_deviation) (void *priv, s16 dev, int flag);
+	int (*pll_set) (void *priv, void *priv_params,
+			u8 pll_addr, u8 demoda_addr, s32 * off);
+	 s16(*osc_deviation) (void *priv, s16 dev, int flag);
 };
 
 extern
diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
index b19a037e692..9453929d0d1 100644
--- a/drivers/media/dvb/frontends/drxd_firm.c
+++ b/drivers/media/dvb/frontends/drxd_firm.c
@@ -44,292 +44,294 @@
 /* HI firmware patches */
 
 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
-#define HI_TR_FUNC_SIZE 9   /* size of this function in instruction words */
-
-u8_t DRXD_InitAtomicRead[] =
-{
-    WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE),
-	0x26, 0x00,  /* 0         -> ring.rdy;           */
-	0x60, 0x04,  /* r0rami.dt -> ring.xba;           */
-	0x61, 0x04,  /* r0rami.dt -> ring.xad;           */
-	0xE3, 0x07,  /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
-	0x40, 0x00,  /* (long immediate)                 */
-	0x64, 0x04,  /* r0rami.dt -> ring.len;           */
-	0x65, 0x04,  /* r0rami.dt -> ring.ctl;           */
-	0x26, 0x00,  /* 0         -> ring.rdy;           */
-	0x38, 0x00,  /* 0         -> jumps.ad;           */
-    END_OF_TABLE
+#define HI_TR_FUNC_SIZE 9	/* size of this function in instruction words */
+
+u8_t DRXD_InitAtomicRead[] = {
+	WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
+	0x26, 0x00,		/* 0         -> ring.rdy;           */
+	0x60, 0x04,		/* r0rami.dt -> ring.xba;           */
+	0x61, 0x04,		/* r0rami.dt -> ring.xad;           */
+	0xE3, 0x07,		/* HI_RA_RAM_USR_BEGIN -> ring.iad; */
+	0x40, 0x00,		/* (long immediate)                 */
+	0x64, 0x04,		/* r0rami.dt -> ring.len;           */
+	0x65, 0x04,		/* r0rami.dt -> ring.ctl;           */
+	0x26, 0x00,		/* 0         -> ring.rdy;           */
+	0x38, 0x00,		/* 0         -> jumps.ad;           */
+	END_OF_TABLE
 };
 
 /* Pins D0 and D1 of the parallel MPEG output can be used
    to set the I2C address of a device. */
 
 #define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
-#define HI_RST_FUNC_SIZE 54   /* size of this function in instruction words */
+#define HI_RST_FUNC_SIZE 54	/* size of this function in instruction words */
 
 /* D0 Version */
-u8_t DRXD_HiI2cPatch_1[] =
-{
-    WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
-	0xC8, 0x07, 0x01, 0x00,  /* MASK      -> reg0.dt;                        */
-	0xE0, 0x07, 0x15, 0x02,  /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
-	0xE1, 0x07, 0x12, 0x00,  /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
-	0xA2, 0x00,              /* M_BNK_ID_DAT -> ring.iba;                    */
-	0x23, 0x00,              /* &data     -> ring.iad;                       */
-	0x24, 0x00,              /* 0         -> ring.len;                       */
-	0xA5, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0x42, 0x00,              /* &data+1   -> w0ram.ad;                       */
-	0xC0, 0x07, 0xFF, 0x0F,  /* -1        -> w0ram.dt;                       */
-	0x63, 0x00,              /* &data+1   -> ring.iad;                       */
-	0x65, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0xE1, 0x07, 0x38, 0x00,  /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
-	0xA5, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0xE1, 0x07, 0x12, 0x00,  /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
-	0x23, 0x00,              /* &data     -> ring.iad;                       */
-	0x65, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0x42, 0x00,              /* &data+1   -> w0ram.ad;                       */
-	0x0F, 0x04,              /* r0ram.dt  -> and.op;                         */
-	0x1C, 0x06,              /* reg0.dt   -> and.tr;                         */
-	0xCF, 0x04,              /* and.rs    -> add.op;                         */
-	0xD0, 0x07, 0x70, 0x00,  /* DEF_DEV_ID -> add.tr;                        */
-	0xD0, 0x04,              /* add.rs    -> add.tr;                         */
-	0xC8, 0x04,              /* add.rs    -> reg0.dt;                        */
-	0x60, 0x00,              /* reg0.dt   -> w0ram.dt;                       */
-	0xC2, 0x07, 0x10, 0x00,  /* SLV0_BASE -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x06,              /* reg0.dt   -> w0rami.dt;                      */
-	0xC2, 0x07, 0x20, 0x00,  /* SLV1_BASE -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x06,              /* reg0.dt   -> w0rami.dt;                      */
-	0xC2, 0x07, 0x30, 0x00,  /* CMD_BASE  -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x68, 0x00,              /* M_IC_SEL_PT1 -> i2c.sel;                     */
-	0x29, 0x00,              /* M_IC_CMD_RESET -> i2c.cmd;                   */
-	0x28, 0x00,              /* M_IC_SEL_PT0 -> i2c.sel;                     */
-	0x29, 0x00,              /* M_IC_CMD_RESET -> i2c.cmd;                   */
-	0xF8, 0x07, 0x2F, 0x00,  /* 0x2F      -> jumps.ad;                       */
-
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-
-    /* Force quick and dirty reset */
-    WR16(B_HI_CT_REG_COMM_STATE__A,0),
-    END_OF_TABLE
+u8_t DRXD_HiI2cPatch_1[] = {
+	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
+	0xC8, 0x07, 0x01, 0x00,	/* MASK      -> reg0.dt;                        */
+	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
+	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
+	0xA2, 0x00,		/* M_BNK_ID_DAT -> ring.iba;                    */
+	0x23, 0x00,		/* &data     -> ring.iad;                       */
+	0x24, 0x00,		/* 0         -> ring.len;                       */
+	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
+	0xC0, 0x07, 0xFF, 0x0F,	/* -1        -> w0ram.dt;                       */
+	0x63, 0x00,		/* &data+1   -> ring.iad;                       */
+	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0xE1, 0x07, 0x38, 0x00,	/* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
+	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
+	0x23, 0x00,		/* &data     -> ring.iad;                       */
+	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
+	0x0F, 0x04,		/* r0ram.dt  -> and.op;                         */
+	0x1C, 0x06,		/* reg0.dt   -> and.tr;                         */
+	0xCF, 0x04,		/* and.rs    -> add.op;                         */
+	0xD0, 0x07, 0x70, 0x00,	/* DEF_DEV_ID -> add.tr;                        */
+	0xD0, 0x04,		/* add.rs    -> add.tr;                         */
+	0xC8, 0x04,		/* add.rs    -> reg0.dt;                        */
+	0x60, 0x00,		/* reg0.dt   -> w0ram.dt;                       */
+	0xC2, 0x07, 0x10, 0x00,	/* SLV0_BASE -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
+	0xC2, 0x07, 0x20, 0x00,	/* SLV1_BASE -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
+	0xC2, 0x07, 0x30, 0x00,	/* CMD_BASE  -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x68, 0x00,		/* M_IC_SEL_PT1 -> i2c.sel;                     */
+	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
+	0x28, 0x00,		/* M_IC_SEL_PT0 -> i2c.sel;                     */
+	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
+	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */
+
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+
+	/* Force quick and dirty reset */
+	WR16(B_HI_CT_REG_COMM_STATE__A, 0),
+	END_OF_TABLE
 };
 
 /* D0,D1 Version */
-u8_t DRXD_HiI2cPatch_3[] =
-{
-    WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
-	0xC8, 0x07, 0x03, 0x00,  /* MASK      -> reg0.dt;                        */
-	0xE0, 0x07, 0x15, 0x02,  /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
-	0xE1, 0x07, 0x12, 0x00,  /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
-	0xA2, 0x00,              /* M_BNK_ID_DAT -> ring.iba;                    */
-	0x23, 0x00,              /* &data     -> ring.iad;                       */
-	0x24, 0x00,              /* 0         -> ring.len;                       */
-	0xA5, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0x42, 0x00,              /* &data+1   -> w0ram.ad;                       */
-	0xC0, 0x07, 0xFF, 0x0F,  /* -1        -> w0ram.dt;                       */
-	0x63, 0x00,              /* &data+1   -> ring.iad;                       */
-	0x65, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0xE1, 0x07, 0x38, 0x00,  /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
-	0xA5, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0xE1, 0x07, 0x12, 0x00,  /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
-	0x23, 0x00,              /* &data     -> ring.iad;                       */
-	0x65, 0x02,              /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
-	0x26, 0x00,              /* 0         -> ring.rdy;                       */
-	0x42, 0x00,              /* &data+1   -> w0ram.ad;                       */
-	0x0F, 0x04,              /* r0ram.dt  -> and.op;                         */
-	0x1C, 0x06,              /* reg0.dt   -> and.tr;                         */
-	0xCF, 0x04,              /* and.rs    -> add.op;                         */
-	0xD0, 0x07, 0x70, 0x00,  /* DEF_DEV_ID -> add.tr;                        */
-	0xD0, 0x04,              /* add.rs    -> add.tr;                         */
-	0xC8, 0x04,              /* add.rs    -> reg0.dt;                        */
-	0x60, 0x00,              /* reg0.dt   -> w0ram.dt;                       */
-	0xC2, 0x07, 0x10, 0x00,  /* SLV0_BASE -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x06,              /* reg0.dt   -> w0rami.dt;                      */
-	0xC2, 0x07, 0x20, 0x00,  /* SLV1_BASE -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x06,              /* reg0.dt   -> w0rami.dt;                      */
-	0xC2, 0x07, 0x30, 0x00,  /* CMD_BASE  -> w0rami.ad;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x01, 0x00,              /* 0         -> w0rami.dt;                      */
-	0x68, 0x00,              /* M_IC_SEL_PT1 -> i2c.sel;                     */
-	0x29, 0x00,              /* M_IC_CMD_RESET -> i2c.cmd;                   */
-	0x28, 0x00,              /* M_IC_SEL_PT0 -> i2c.sel;                     */
-	0x29, 0x00,              /* M_IC_CMD_RESET -> i2c.cmd;                   */
-	0xF8, 0x07, 0x2F, 0x00,  /* 0x2F      -> jumps.ad;                       */
-
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
-
-    /* Force quick and dirty reset */
-    WR16(B_HI_CT_REG_COMM_STATE__A,0),
-    END_OF_TABLE
+u8_t DRXD_HiI2cPatch_3[] = {
+	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
+	0xC8, 0x07, 0x03, 0x00,	/* MASK      -> reg0.dt;                        */
+	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
+	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
+	0xA2, 0x00,		/* M_BNK_ID_DAT -> ring.iba;                    */
+	0x23, 0x00,		/* &data     -> ring.iad;                       */
+	0x24, 0x00,		/* 0         -> ring.len;                       */
+	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
+	0xC0, 0x07, 0xFF, 0x0F,	/* -1        -> w0ram.dt;                       */
+	0x63, 0x00,		/* &data+1   -> ring.iad;                       */
+	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0xE1, 0x07, 0x38, 0x00,	/* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
+	0xA5, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0xE1, 0x07, 0x12, 0x00,	/* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
+	0x23, 0x00,		/* &data     -> ring.iad;                       */
+	0x65, 0x02,		/* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
+	0x26, 0x00,		/* 0         -> ring.rdy;                       */
+	0x42, 0x00,		/* &data+1   -> w0ram.ad;                       */
+	0x0F, 0x04,		/* r0ram.dt  -> and.op;                         */
+	0x1C, 0x06,		/* reg0.dt   -> and.tr;                         */
+	0xCF, 0x04,		/* and.rs    -> add.op;                         */
+	0xD0, 0x07, 0x70, 0x00,	/* DEF_DEV_ID -> add.tr;                        */
+	0xD0, 0x04,		/* add.rs    -> add.tr;                         */
+	0xC8, 0x04,		/* add.rs    -> reg0.dt;                        */
+	0x60, 0x00,		/* reg0.dt   -> w0ram.dt;                       */
+	0xC2, 0x07, 0x10, 0x00,	/* SLV0_BASE -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
+	0xC2, 0x07, 0x20, 0x00,	/* SLV1_BASE -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x06,		/* reg0.dt   -> w0rami.dt;                      */
+	0xC2, 0x07, 0x30, 0x00,	/* CMD_BASE  -> w0rami.ad;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x01, 0x00,		/* 0         -> w0rami.dt;                      */
+	0x68, 0x00,		/* M_IC_SEL_PT1 -> i2c.sel;                     */
+	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
+	0x28, 0x00,		/* M_IC_SEL_PT0 -> i2c.sel;                     */
+	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */
+	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */
+
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
+	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+
+	/* Force quick and dirty reset */
+	WR16(B_HI_CT_REG_COMM_STATE__A, 0),
+	END_OF_TABLE
 };
 
-u8_t DRXD_ResetCEFR[] =
-{
-   WRBLOCK(CE_REG_FR_TREAL00__A, 57),
-      0x52,0x00, /* CE_REG_FR_TREAL00__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG00__A */
-      0x52,0x00, /* CE_REG_FR_TREAL01__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG01__A */
-      0x52,0x00, /* CE_REG_FR_TREAL02__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG02__A */
-      0x52,0x00, /* CE_REG_FR_TREAL03__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG03__A */
-      0x52,0x00, /* CE_REG_FR_TREAL04__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG04__A */
-      0x52,0x00, /* CE_REG_FR_TREAL05__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG05__A */
-      0x52,0x00, /* CE_REG_FR_TREAL06__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG06__A */
-      0x52,0x00, /* CE_REG_FR_TREAL07__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG07__A */
-      0x52,0x00, /* CE_REG_FR_TREAL08__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG08__A */
-      0x52,0x00, /* CE_REG_FR_TREAL09__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG09__A */
-      0x52,0x00, /* CE_REG_FR_TREAL10__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG10__A */
-      0x52,0x00, /* CE_REG_FR_TREAL11__A */
-      0x00,0x00, /* CE_REG_FR_TIMAG11__A */
-
-      0x52,0x00, /* CE_REG_FR_MID_TAP__A */
-
-      0x0B,0x00, /* CE_REG_FR_SQS_G00__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G01__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G02__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G03__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G04__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G05__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G06__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G07__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G08__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G09__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G10__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G11__A */
-      0x0B,0x00, /* CE_REG_FR_SQS_G12__A */
-
-      0xFF,0x01, /* CE_REG_FR_RIO_G00__A */
-      0x90,0x01, /* CE_REG_FR_RIO_G01__A */
-      0x0B,0x01, /* CE_REG_FR_RIO_G02__A */
-      0xC8,0x00, /* CE_REG_FR_RIO_G03__A */
-      0xA0,0x00, /* CE_REG_FR_RIO_G04__A */
-      0x85,0x00, /* CE_REG_FR_RIO_G05__A */
-      0x72,0x00, /* CE_REG_FR_RIO_G06__A */
-      0x64,0x00, /* CE_REG_FR_RIO_G07__A */
-      0x59,0x00, /* CE_REG_FR_RIO_G08__A */
-      0x50,0x00, /* CE_REG_FR_RIO_G09__A */
-      0x49,0x00, /* CE_REG_FR_RIO_G10__A */
-
-      0x10,0x00, /* CE_REG_FR_MODE__A     */
-      0x78,0x00, /* CE_REG_FR_SQS_TRH__A  */
-      0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */
-      0x00,0x02, /* CE_REG_FR_BYPASS__A   */
-      0x0D,0x00, /* CE_REG_FR_PM_SET__A   */
-      0x07,0x00, /* CE_REG_FR_ERR_SH__A   */
-      0x04,0x00, /* CE_REG_FR_MAN_SH__A   */
-      0x06,0x00, /* CE_REG_FR_TAP_SH__A   */
-
-   END_OF_TABLE
+u8_t DRXD_ResetCEFR[] = {
+	WRBLOCK(CE_REG_FR_TREAL00__A, 57),
+	0x52, 0x00,		/* CE_REG_FR_TREAL00__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG00__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL01__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG01__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL02__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG02__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL03__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG03__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL04__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG04__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL05__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG05__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL06__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG06__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL07__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG07__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL08__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG08__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL09__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG09__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL10__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG10__A */
+	0x52, 0x00,		/* CE_REG_FR_TREAL11__A */
+	0x00, 0x00,		/* CE_REG_FR_TIMAG11__A */
+
+	0x52, 0x00,		/* CE_REG_FR_MID_TAP__A */
+
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G00__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G01__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G02__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G03__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G04__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G05__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G06__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G07__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G08__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G09__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G10__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G11__A */
+	0x0B, 0x00,		/* CE_REG_FR_SQS_G12__A */
+
+	0xFF, 0x01,		/* CE_REG_FR_RIO_G00__A */
+	0x90, 0x01,		/* CE_REG_FR_RIO_G01__A */
+	0x0B, 0x01,		/* CE_REG_FR_RIO_G02__A */
+	0xC8, 0x00,		/* CE_REG_FR_RIO_G03__A */
+	0xA0, 0x00,		/* CE_REG_FR_RIO_G04__A */
+	0x85, 0x00,		/* CE_REG_FR_RIO_G05__A */
+	0x72, 0x00,		/* CE_REG_FR_RIO_G06__A */
+	0x64, 0x00,		/* CE_REG_FR_RIO_G07__A */
+	0x59, 0x00,		/* CE_REG_FR_RIO_G08__A */
+	0x50, 0x00,		/* CE_REG_FR_RIO_G09__A */
+	0x49, 0x00,		/* CE_REG_FR_RIO_G10__A */
+
+	0x10, 0x00,		/* CE_REG_FR_MODE__A     */
+	0x78, 0x00,		/* CE_REG_FR_SQS_TRH__A  */
+	0x00, 0x00,		/* CE_REG_FR_RIO_GAIN__A */
+	0x00, 0x02,		/* CE_REG_FR_BYPASS__A   */
+	0x0D, 0x00,		/* CE_REG_FR_PM_SET__A   */
+	0x07, 0x00,		/* CE_REG_FR_ERR_SH__A   */
+	0x04, 0x00,		/* CE_REG_FR_MAN_SH__A   */
+	0x06, 0x00,		/* CE_REG_FR_TAP_SH__A   */
+
+	END_OF_TABLE
 };
 
-
-u8_t DRXD_InitFEA2_1[] =
-{
-   WRBLOCK(FE_AD_REG_PD__A , 3),
-      0x00,0x00, /* FE_AD_REG_PD__A          */
-      0x01,0x00, /* FE_AD_REG_INVEXT__A      */
-      0x00,0x00, /* FE_AD_REG_CLKNEG__A      */
-
-   WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A ,  2),
-      0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
-      0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
-
-   WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A   ,  2),
-      0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
-      0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
-
-   WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A   , 5),
-      0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
-      0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
-      0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
-      0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */
-      0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
-
-   WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A   ,  2),
-      0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
-      0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
-
-   WRBLOCK(FE_AG_REG_IND_WIN__A  ,  29),
-      0x00,0x00, /* FE_AG_REG_IND_WIN__A     */
-      0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */
-      0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */
-      0x00,0x00, /* FE_AG_REG_IND_DEL__A     don't care */
-      0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */
-      0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
-      0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
-      0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care  */
-      0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
-      0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */
-      0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
-      0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care  */
-      0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
-      0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
-      0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care  */
-      0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care  */
-      0x02,0x00, /* FE_AG_REG_PDC_MAX__A     */
-      0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
-      0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
-      0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care  */
-      0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
-      0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */
-      0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
-      0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care  */
-      0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */
-      0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */
-      0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care  */
-      0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
-      0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
-
-   WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A   , 2),
-      0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
-      0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
-
-   WRBLOCK(FE_FD_REG_SCL__A           , 3),
-      0x05,0x00, /* FE_FD_REG_SCL__A         */
-      0x03,0x00, /* FE_FD_REG_MAX_LEV__A     */
-      0x05,0x00, /* FE_FD_REG_NR__A          */
-
-   WRBLOCK(FE_CF_REG_SCL__A           , 5),
-      0x16,0x00, /* FE_CF_REG_SCL__A         */
-      0x04,0x00, /* FE_CF_REG_MAX_LEV__A     */
-      0x06,0x00, /* FE_CF_REG_NR__A          */
-      0x00,0x00, /* FE_CF_REG_IMP_VAL__A     */
-      0x01,0x00, /* FE_CF_REG_MEAS_VAL__A    */
-
-   WRBLOCK(FE_CU_REG_FRM_CNT_RST__A   , 2),
-      0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */
-      0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */
-
-   END_OF_TABLE
+u8_t DRXD_InitFEA2_1[] = {
+	WRBLOCK(FE_AD_REG_PD__A, 3),
+	0x00, 0x00,		/* FE_AD_REG_PD__A          */
+	0x01, 0x00,		/* FE_AD_REG_INVEXT__A      */
+	0x00, 0x00,		/* FE_AD_REG_CLKNEG__A      */
+
+	WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
+	0x10, 0x00,		/* FE_AG_REG_DCE_AUR_CNT__A */
+	0x10, 0x00,		/* FE_AG_REG_DCE_RUR_CNT__A */
+
+	WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
+	0x0E, 0x00,		/* FE_AG_REG_ACE_AUR_CNT__A */
+	0x00, 0x00,		/* FE_AG_REG_ACE_RUR_CNT__A */
+
+	WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
+	0x04, 0x00,		/* FE_AG_REG_EGC_FLA_RGN__A */
+	0x1F, 0x00,		/* FE_AG_REG_EGC_SLO_RGN__A */
+	0x00, 0x00,		/* FE_AG_REG_EGC_JMP_PSN__A */
+	0x00, 0x00,		/* FE_AG_REG_EGC_FLA_INC__A */
+	0x00, 0x00,		/* FE_AG_REG_EGC_FLA_DEC__A */
+
+	WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
+	0xFF, 0x01,		/* FE_AG_REG_GC1_AGC_MAX__A */
+	0x00, 0xFE,		/* FE_AG_REG_GC1_AGC_MIN__A */
+
+	WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
+	0x00, 0x00,		/* FE_AG_REG_IND_WIN__A     */
+	0x05, 0x00,		/* FE_AG_REG_IND_THD_LOL__A */
+	0x0F, 0x00,		/* FE_AG_REG_IND_THD_HIL__A */
+	0x00, 0x00,		/* FE_AG_REG_IND_DEL__A     don't care */
+	0x1E, 0x00,		/* FE_AG_REG_IND_PD1_WRI__A */
+	0x0C, 0x00,		/* FE_AG_REG_PDA_AUR_CNT__A */
+	0x00, 0x00,		/* FE_AG_REG_PDA_RUR_CNT__A */
+	0x00, 0x00,		/* FE_AG_REG_PDA_AVE_DAT__A don't care  */
+	0x00, 0x00,		/* FE_AG_REG_PDC_RUR_CNT__A */
+	0x01, 0x00,		/* FE_AG_REG_PDC_SET_LVL__A */
+	0x02, 0x00,		/* FE_AG_REG_PDC_FLA_RGN__A */
+	0x00, 0x00,		/* FE_AG_REG_PDC_JMP_PSN__A don't care  */
+	0xFF, 0xFF,		/* FE_AG_REG_PDC_FLA_STP__A */
+	0xFF, 0xFF,		/* FE_AG_REG_PDC_SLO_STP__A */
+	0x00, 0x1F,		/* FE_AG_REG_PDC_PD2_WRI__A don't care  */
+	0x00, 0x00,		/* FE_AG_REG_PDC_MAP_DAT__A don't care  */
+	0x02, 0x00,		/* FE_AG_REG_PDC_MAX__A     */
+	0x0C, 0x00,		/* FE_AG_REG_TGA_AUR_CNT__A */
+	0x00, 0x00,		/* FE_AG_REG_TGA_RUR_CNT__A */
+	0x00, 0x00,		/* FE_AG_REG_TGA_AVE_DAT__A don't care  */
+	0x00, 0x00,		/* FE_AG_REG_TGC_RUR_CNT__A */
+	0x22, 0x00,		/* FE_AG_REG_TGC_SET_LVL__A */
+	0x15, 0x00,		/* FE_AG_REG_TGC_FLA_RGN__A */
+	0x00, 0x00,		/* FE_AG_REG_TGC_JMP_PSN__A don't care  */
+	0x01, 0x00,		/* FE_AG_REG_TGC_FLA_STP__A */
+	0x0A, 0x00,		/* FE_AG_REG_TGC_SLO_STP__A */
+	0x00, 0x00,		/* FE_AG_REG_TGC_MAP_DAT__A don't care  */
+	0x10, 0x00,		/* FE_AG_REG_FGA_AUR_CNT__A */
+	0x10, 0x00,		/* FE_AG_REG_FGA_RUR_CNT__A */
+
+	WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
+	0x00, 0x00,		/* FE_AG_REG_BGC_FGC_WRI__A */
+	0x00, 0x00,		/* FE_AG_REG_BGC_CGC_WRI__A */
+
+	WRBLOCK(FE_FD_REG_SCL__A, 3),
+	0x05, 0x00,		/* FE_FD_REG_SCL__A         */
+	0x03, 0x00,		/* FE_FD_REG_MAX_LEV__A     */
+	0x05, 0x00,		/* FE_FD_REG_NR__A          */
+
+	WRBLOCK(FE_CF_REG_SCL__A, 5),
+	0x16, 0x00,		/* FE_CF_REG_SCL__A         */
+	0x04, 0x00,		/* FE_CF_REG_MAX_LEV__A     */
+	0x06, 0x00,		/* FE_CF_REG_NR__A          */
+	0x00, 0x00,		/* FE_CF_REG_IMP_VAL__A     */
+	0x01, 0x00,		/* FE_CF_REG_MEAS_VAL__A    */
+
+	WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
+	0x00, 0x08,		/* FE_CU_REG_FRM_CNT_RST__A */
+	0x00, 0x00,		/* FE_CU_REG_FRM_CNT_STR__A */
+
+	END_OF_TABLE
 };
 
    /* with PGA */
@@ -339,603 +341,589 @@ u8_t DRXD_InitFEA2_1[] =
 /*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
 /*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
 
-u8_t DRXD_InitFEA2_2[] =
-{
-   WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
-   WR16(FE_AG_REG_FGM_WRI__A    ,     48),
-   /* Activate measurement, activate scale */
-   WR16(FE_FD_REG_MEAS_VAL__A , 0x0001),
-
-   WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
-   WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
-   WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
-   WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
-   WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
-   WR16(FE_AD_REG_COMM_EXEC__A     , 0x0001),
-   WR16(FE_AG_REG_COMM_EXEC__A     , 0x0001),
-   WR16(FE_AG_REG_AG_MODE_LOP__A   , 0x895E),
-
-   END_OF_TABLE
+u8_t DRXD_InitFEA2_2[] = {
+	WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
+	WR16(FE_AG_REG_FGM_WRI__A, 48),
+	/* Activate measurement, activate scale */
+	WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
+
+	WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
+	WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
+
+	END_OF_TABLE
 };
 
-u8_t DRXD_InitFEB1_1[] =
-{
-   WR16(B_FE_AD_REG_PD__A            ,0x0000 ),
-   WR16(B_FE_AD_REG_CLKNEG__A        ,0x0000 ),
-   WR16(B_FE_AG_REG_BGC_FGC_WRI__A   ,0x0000 ),
-   WR16(B_FE_AG_REG_BGC_CGC_WRI__A   ,0x0000 ),
-   WR16(B_FE_AG_REG_AG_MODE_LOP__A   ,0x000a ),
-   WR16(B_FE_AG_REG_IND_PD1_WRI__A   ,35     ),
-   WR16(B_FE_AG_REG_IND_WIN__A       ,0      ),
-   WR16(B_FE_AG_REG_IND_THD_LOL__A   ,8      ),
-   WR16(B_FE_AG_REG_IND_THD_HIL__A   ,8      ),
-   WR16(B_FE_CF_REG_IMP_VAL__A       ,1      ),
-   WR16(B_FE_AG_REG_EGC_FLA_RGN__A   ,7      ),
-   END_OF_TABLE
+u8_t DRXD_InitFEB1_1[] = {
+	WR16(B_FE_AD_REG_PD__A, 0x0000),
+	WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
+	WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
+	WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
+	WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
+	WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
+	WR16(B_FE_AG_REG_IND_WIN__A, 0),
+	WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
+	WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
+	WR16(B_FE_CF_REG_IMP_VAL__A, 1),
+	WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
+	END_OF_TABLE
 };
+
 	/* with PGA */
 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   , 0x0000, 0x0000); */
        /* without PGA */
 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   ,
 	     B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
-/*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/
+									     /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
 /*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
 
-u8_t DRXD_InitFEB1_2[] =
-{
-   WR16(B_FE_COMM_EXEC__A          ,0x0001  ),
-
-   /* RF-AGC setup */
-   WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C   ),
-   WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01   ),
-   WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02   ),
-   WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ),
-   WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ),
-   WR16(B_FE_AG_REG_PDC_MAX__A     , 0x02   ),
-   WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C   ),
-   WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22   ),
-   WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15   ),
-   WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01   ),
-   WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A   ),
-
-   WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0      ),
-   WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000  ),
-   WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1      ),
-   END_OF_TABLE
+u8_t DRXD_InitFEB1_2[] = {
+	WR16(B_FE_COMM_EXEC__A, 0x0001),
+
+	/* RF-AGC setup */
+	WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
+	WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
+	WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
+	WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
+	WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
+	WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
+	WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
+	WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
+	WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
+	WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
+	WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
+
+	WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
+	WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
+	WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
+	END_OF_TABLE
 };
 
-u8_t DRXD_InitCPA2[] =
-{
-   WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2),
-      0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A  */
-      0x0A,0x00, /* CP_REG_BR_STR_DEL__A     */
-
-   WRBLOCK(CP_REG_RT_ANG_INC0__A   , 4),
-      0x00,0x00, /* CP_REG_RT_ANG_INC0__A    */
-      0x00,0x00, /* CP_REG_RT_ANG_INC1__A    */
-      0x03,0x00, /* CP_REG_RT_DETECT_ENA__A  */
-      0x03,0x00, /* CP_REG_RT_DETECT_TRH__A  */
-
-   WRBLOCK(CP_REG_AC_NEXP_OFFS__A  , 5),
-      0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A   */
-      0x62,0x00, /* CP_REG_AC_AVER_POW__A    */
-      0x82,0x00, /* CP_REG_AC_MAX_POW__A     */
-      0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A  */
-      0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A  */
-
-   WRBLOCK(CP_REG_AC_AMP_MODE__A   ,2),
-      0x02,0x00, /* CP_REG_AC_AMP_MODE__A    */
-      0x01,0x00, /* CP_REG_AC_AMP_FIX__A     */
-
-   WR16(CP_REG_INTERVAL__A         , 0x0005 ),
-   WR16(CP_REG_RT_EXP_MARG__A      , 0x0004 ),
-   WR16(CP_REG_AC_ANG_MODE__A      , 0x0003 ),
-
-   WR16(CP_REG_COMM_EXEC__A        , 0x0001 ),
-   END_OF_TABLE
+u8_t DRXD_InitCPA2[] = {
+	WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
+	0x07, 0x00,		/* CP_REG_BR_SPL_OFFSET__A  */
+	0x0A, 0x00,		/* CP_REG_BR_STR_DEL__A     */
+
+	WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
+	0x00, 0x00,		/* CP_REG_RT_ANG_INC0__A    */
+	0x00, 0x00,		/* CP_REG_RT_ANG_INC1__A    */
+	0x03, 0x00,		/* CP_REG_RT_DETECT_ENA__A  */
+	0x03, 0x00,		/* CP_REG_RT_DETECT_TRH__A  */
+
+	WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
+	0x32, 0x00,		/* CP_REG_AC_NEXP_OFFS__A   */
+	0x62, 0x00,		/* CP_REG_AC_AVER_POW__A    */
+	0x82, 0x00,		/* CP_REG_AC_MAX_POW__A     */
+	0x26, 0x00,		/* CP_REG_AC_WEIGHT_MAN__A  */
+	0x0F, 0x00,		/* CP_REG_AC_WEIGHT_EXP__A  */
+
+	WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
+	0x02, 0x00,		/* CP_REG_AC_AMP_MODE__A    */
+	0x01, 0x00,		/* CP_REG_AC_AMP_FIX__A     */
+
+	WR16(CP_REG_INTERVAL__A, 0x0005),
+	WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
+	WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
+
+	WR16(CP_REG_COMM_EXEC__A, 0x0001),
+	END_OF_TABLE
 };
 
-u8_t DRXD_InitCPB1[] =
-{
-   WR16(B_CP_REG_BR_SPL_OFFSET__A    ,0x0008 ),
-   WR16(B_CP_COMM_EXEC__A            ,0x0001 ),
-   END_OF_TABLE
+u8_t DRXD_InitCPB1[] = {
+	WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
+	WR16(B_CP_COMM_EXEC__A, 0x0001),
+	END_OF_TABLE
 };
 
+u8_t DRXD_InitCEA2[] = {
+	WRBLOCK(CE_REG_AVG_POW__A, 4),
+	0x62, 0x00,		/* CE_REG_AVG_POW__A        */
+	0x78, 0x00,		/* CE_REG_MAX_POW__A        */
+	0x62, 0x00,		/* CE_REG_ATT__A            */
+	0x17, 0x00,		/* CE_REG_NRED__A           */
 
-u8_t DRXD_InitCEA2[] =
-{
-   WRBLOCK(CE_REG_AVG_POW__A          , 4),
-      0x62,0x00, /* CE_REG_AVG_POW__A        */
-      0x78,0x00, /* CE_REG_MAX_POW__A        */
-      0x62,0x00, /* CE_REG_ATT__A            */
-      0x17,0x00, /* CE_REG_NRED__A           */
-
-   WRBLOCK(CE_REG_NE_ERR_SELECT__A    , 2),
-      0x07,0x00, /* CE_REG_NE_ERR_SELECT__A  */
-      0xEB,0xFF, /* CE_REG_NE_TD_CAL__A      */
+	WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
+	0x07, 0x00,		/* CE_REG_NE_ERR_SELECT__A  */
+	0xEB, 0xFF,		/* CE_REG_NE_TD_CAL__A      */
 
-   WRBLOCK(CE_REG_NE_MIXAVG__A        , 2),
-      0x06,0x00, /* CE_REG_NE_MIXAVG__A      */
-      0x00,0x00, /* CE_REG_NE_NUPD_OFS__A    */
+	WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
+	0x06, 0x00,		/* CE_REG_NE_MIXAVG__A      */
+	0x00, 0x00,		/* CE_REG_NE_NUPD_OFS__A    */
 
-   WRBLOCK(CE_REG_PE_NEXP_OFFS__A     , 2),
-      0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A   */
-      0x00,0x00, /* CE_REG_PE_TIMESHIFT__A   */
+	WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
+	0x00, 0x00,		/* CE_REG_PE_NEXP_OFFS__A   */
+	0x00, 0x00,		/* CE_REG_PE_TIMESHIFT__A   */
 
-   WRBLOCK(CE_REG_TP_A0_TAP_NEW__A    , 3),
-      0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A       */
-      0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
-      0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A   */
+	WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
+	0x00, 0x01,		/* CE_REG_TP_A0_TAP_NEW__A       */
+	0x01, 0x00,		/* CE_REG_TP_A0_TAP_NEW_VALID__A */
+	0x0E, 0x00,		/* CE_REG_TP_A0_MU_LMS_STEP__A   */
 
-   WRBLOCK(CE_REG_TP_A1_TAP_N