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authorDave Olson <dave.olson@qlogic.com>2010-06-17 23:13:44 +0000
committerRoland Dreier <rolandd@cisco.com>2010-07-06 14:13:20 -0700
commitfce24a9d28f8b99fd0eacc14e252ab4fca9527a7 (patch)
tree590717ce8bd0e8a63e072b4bd79b99be69c3b8c8 /drivers/infiniband/hw/qib/qib_iba7322.c
parent67a3e12b05e055c0415c556a315a3d3eb637e29e (diff)
IB/qib: Don't mark VL15 bufs as WC to avoid a rare 7322 chip problem
Don't set write combining via PAT on the VL15 buffers to avoid a rare problem with unaligned writes from interrupt-flushed store buffers. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/qib/qib_iba7322.c')
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7322.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index 503992d9c5c..3e9828be501 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -6119,9 +6119,25 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
qib_set_ctxtcnt(dd);
if (qib_wc_pat) {
- ret = init_chip_wc_pat(dd, NUM_VL15_BUFS * dd->align4k);
+ resource_size_t vl15off;
+ /*
+ * We do not set WC on the VL15 buffers to avoid
+ * a rare problem with unaligned writes from
+ * interrupt-flushed store buffers, so we need
+ * to map those separately here. We can't solve
+ * this for the rarely used mtrr case.
+ */
+ ret = init_chip_wc_pat(dd, 0);
if (ret)
goto bail;
+
+ /* vl15 buffers start just after the 4k buffers */
+ vl15off = dd->physaddr + (dd->piobufbase >> 32) +
+ dd->piobcnt4k * dd->align4k;
+ dd->piovl15base = ioremap_nocache(vl15off,
+ NUM_VL15_BUFS * dd->align4k);
+ if (!dd->piovl15base)
+ goto bail;
}
qib_7322_set_baseaddrs(dd); /* set chip access pointers now */