diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-09-13 09:57:50 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-09-15 20:27:49 -0400 |
| commit | ce7b30e02578dda6b2263b05308c640f3b57d32c (patch) | |
| tree | a2a80afda62aae00b89c3ebd64d9b4f803654fb1 /drivers/gpu | |
| parent | c3eaa088277709d3e489c19a5a5b698eefbeb434 (diff) | |
drm/radeon/dpm/rs780: add some sanity checking to sclk scaling
Since the clock scaling is based on fb divider adjustments,
make sure the other pll parameters are the same.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/rs780_dpm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c index afb75845c16..31487ce294c 100644 --- a/drivers/gpu/drm/radeon/rs780_dpm.c +++ b/drivers/gpu/drm/radeon/rs780_dpm.c @@ -449,6 +449,12 @@ static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, if (ret) return ret; + if ((min_dividers.ref_div != max_dividers.ref_div) || + (min_dividers.post_div != max_dividers.post_div) || + (max_dividers.ref_div != current_max_dividers.ref_div) || + (max_dividers.post_div != current_max_dividers.post_div)) + return -EINVAL; + rs780_force_fbdiv(rdev, max_dividers.fb_div); if (max_dividers.fb_div > min_dividers.fb_div) { |