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authorChristian König <deathsimple@vodafone.de>2013-04-08 12:41:37 +0200
committerAlex Deucher <alexander.deucher@amd.com>2013-04-09 10:31:39 -0400
commit9a21059dc4c0e80f2eebcb0a9096721ef1dc9c9d (patch)
tree7f116f62ca35fd09d2cf3949dcf27557ff50060b /drivers/gpu/drm/radeon/si.c
parentec5891fbe1b078b191b25a13a2cc40b58fb7a693 (diff)
drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 465053d461b..e9663200cac 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1769,6 +1769,9 @@ static void si_gpu_init(struct radeon_device *rdev)
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
si_tiling_mode_table_init(rdev);