diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-10 17:26:46 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 13:12:47 +1000 |
commit | 70790f4f819875e8f390871fd15bbbf823f28e1b (patch) | |
tree | 47949ac5a0af23a9fe1ace1ac5fd8b8823b8e055 /drivers/gpu/drm/nouveau/nv50_pm.c | |
parent | 8aceb7de47ea2491abc1a577dc875b19e9947a54 (diff) |
drm/nouveau/clock: pull in the implementation from all over the place
Still missing the main bits we use to change performance levels, I'll get
to it after all the hard yakka has been finished.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_pm.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_pm.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c index be5704fd4a8..378ca8ca9d6 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nv50_pm.c @@ -363,7 +363,7 @@ struct nv50_pm_state { }; static u32 -calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, +calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll, u32 clk, int *N1, int *M1, int *log2P) { struct nouveau_pll_vals coef; @@ -373,7 +373,7 @@ calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, if (ret) return 0; - pll->vco2.maxfreq = 0; + pll->vco2.max_freq = 0; pll->refclk = read_pll_ref(dev, reg); if (!pll->refclk) return 0; @@ -542,7 +542,7 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl, .priv = info }; struct hwsq_ucode *hwsq = &info->mclk_hwsq; - struct pll_lims pll; + struct nvbios_pll pll; int N, M, P; int ret; @@ -550,14 +550,14 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl, info->mctrl = nv_rd32(dev, 0x004008); info->mctrl &= ~0x81ff0200; if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) { - info->mctrl |= 0x00000200 | (pll.log2p_bias << 19); + info->mctrl |= 0x00000200 | (pll.bias_p << 19); } else { ret = calc_pll(dev, 0x4008, &pll, perflvl->memory, &N, &M, &P); if (ret == 0) return -EINVAL; info->mctrl |= 0x80000000 | (P << 22) | (P << 16); - info->mctrl |= pll.log2p_bias << 19; + info->mctrl |= pll.bias_p << 19; info->mcoef = (N << 8) | M; } @@ -590,7 +590,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv50_pm_state *info; struct hwsq_ucode *hwsq; - struct pll_lims pll; + struct nvbios_pll pll; u32 out, mast, divs, ctrl; int clk, ret = -EINVAL; int N, M, P1, P2; |