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authorBen Skeggs <bskeggs@redhat.com>2010-03-15 16:43:47 +1000
committerBen Skeggs <bskeggs@redhat.com>2010-04-09 10:11:45 +1000
commit40b2a687bd92827ca144d3623cf48377d8f7680d (patch)
treeb153cf2cace99265ef44e53663f0b63bf8bd343b /drivers/gpu/drm/nouveau/nouveau_sgdma.c
parent0c324971986f1498ccd289cb2b4927a6fd3efbe5 (diff)
drm/nv50: add more 0x100c80 flushy magic
Fixes the !vbo_fifo path in the 3D driver on certain chipsets. Still not really any good idea of what exactly the magic achieves, but it makes things work. While we're at it, in the PCIEGART path, flush on unbinding also. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_sgdma.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index ed1590577b6..554fb45730c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -171,6 +171,24 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
}
dev_priv->engine.instmem.finish_access(nvbe->dev);
+ if (dev_priv->card_type == NV_50) {
+ nv_wr32(dev, 0x100c80, 0x00050001);
+ if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
+ NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
+ NV_ERROR(dev, "0x100c80 = 0x%08x\n",
+ nv_rd32(dev, 0x100c80));
+ return -EBUSY;
+ }
+
+ nv_wr32(dev, 0x100c80, 0x00000001);
+ if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
+ NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
+ NV_ERROR(dev, "0x100c80 = 0x%08x\n",
+ nv_rd32(dev, 0x100c80));
+ return -EBUSY;
+ }
+ }
+
nvbe->bound = false;
return 0;
}