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authorBen Skeggs <bskeggs@redhat.com>2011-12-13 11:57:55 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:05:46 +1000
commitc70c41e89f0481f26749d8264aebc594566c2a6d (patch)
tree9a112ff10ccbda529d70eecbedc5d763113846a0 /drivers/gpu/drm/nouveau/nouveau_drv.h
parent1072856a1c604726be6a8adfb6b2c86033e6a314 (diff)
drm/nv50: hopefully handle the DDR2/DDR3 memtype detection somewhat better
M version 2 appears to have a table with some form of memory type info available. NVIDIA appear to ignore the table information except for this DDR2/DDR3 case (which has the same value in 0x100714). My guess is this is due to some of the supported memory types not being represented in the table. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.h')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 59031d308fc..5a4947919f1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -909,6 +909,7 @@ extern int nouveau_mem_init_agp(struct drm_device *);
extern int nouveau_mem_reset_agp(struct drm_device *);
extern void nouveau_mem_close(struct drm_device *);
extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
+extern int nouveau_mem_vbios_type(struct drm_device *);
extern struct nouveau_tile_reg *nv10_mem_set_tiling(
struct drm_device *dev, uint32_t addr, uint32_t size,
uint32_t pitch, uint32_t flags);