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authorChris Wilson <chris@chris-wilson.co.uk>2010-11-12 13:53:37 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-24 13:30:52 +0000
commitcaea7476d48e5f401f2d18b1738827748fb56c12 (patch)
tree583a60d043ef7c6676499349ad74491e47ce565a /drivers/gpu/drm/i915/i915_drv.h
parenta7a09aebe8c0dd2b76c7b97018a9c614ddb483a5 (diff)
drm/i915: More accurately track last fence usage by the GPU
Based on a patch by Daniel Vetter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h17
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 42d3e901619..ee7df1d2b8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -124,9 +124,8 @@ struct drm_i915_master_private {
#define I915_FENCE_REG_NONE -1
struct drm_i915_fence_reg {
- struct drm_i915_gem_object *obj;
struct list_head lru_list;
- bool gpu;
+ struct drm_i915_gem_object *obj;
};
struct sdvo_device_mapping {
@@ -787,6 +786,12 @@ struct drm_i915_gem_object {
unsigned int fault_mappable : 1;
unsigned int pin_mappable : 1;
+ /*
+ * Is the GPU currently using a fence to access this buffer,
+ */
+ unsigned int pending_fenced_gpu_access:1;
+ unsigned int fenced_gpu_access:1;
+
struct page **pages;
/**
@@ -802,11 +807,13 @@ struct drm_i915_gem_object {
*/
uint32_t gtt_offset;
- /* Which ring is refering to is this object */
- struct intel_ring_buffer *ring;
-
/** Breadcrumb of last rendering to the buffer. */
uint32_t last_rendering_seqno;
+ struct intel_ring_buffer *ring;
+
+ /** Breadcrumb of last fenced GPU access to the buffer. */
+ uint32_t last_fenced_seqno;
+ struct intel_ring_buffer *last_fenced_ring;
/** Current tiling stride for the object, if it's tiled. */
uint32_t stride;