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authorPeter De Schrijver <pdeschrijver@nvidia.com>2014-02-19 20:48:56 +0200
committerPeter De Schrijver <pdeschrijver@nvidia.com>2014-02-20 10:45:28 +0200
commita9952a76bc0c24b3c9d355c053e001b8a3b65dd3 (patch)
tree0c1938aa29534cef5025ef092db0831e0ccc3a0e /drivers/clk
parent3de5bdfb4cb3bd99052a4ffaee358189779be042 (diff)
clk: tegra: Fix vic03 mux index
The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index f5376a3ca53..1fa5c3f33b2 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -371,9 +371,7 @@ static const char *mux_pllp3_pllc_clkm[] = {
static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
};
-static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
- [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
-};
+#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",