Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

1 files changed, 3105 insertions, 0 deletions

diff --git a/drivers/atm/nicstar.c b/drivers/atm/nicstar.c
new file mode 100644
index 00000000000..85bf5c8442b
--- /dev/null
+++ b/drivers/atm/nicstar.c
@@ -0,0 +1,3105 @@
+/******************************************************************************
+ *
+ * nicstar.c
+ *
+ * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
+ *
+ * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
+ *            It was taken from the frle-0.22 device driver.
+ *            As the file doesn't have a copyright notice, in the file
+ *            nicstarmac.copyright I put the copyright notice from the
+ *            frle-0.22 device driver.
+ *            Some code is based on the nicstar driver by M. Welsh.
+ *
+ * Author: Rui Prior (rprior@inescn.pt)
+ * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
+ *
+ *
+ * (C) INESC 1999
+ *
+ *
+ ******************************************************************************/
+
+
+/**** IMPORTANT INFORMATION ***************************************************
+ *
+ * There are currently three types of spinlocks:
+ *
+ * 1 - Per card interrupt spinlock (to protect structures and such)
+ * 2 - Per SCQ scq spinlock
+ * 3 - Per card resource spinlock (to access registers, etc.)
+ *
+ * These must NEVER be grabbed in reverse order.
+ *
+ ******************************************************************************/
+
+/* Header files ***************************************************************/
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <linux/atmdev.h>
+#include <linux/atm.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/atomic.h>
+#include "nicstar.h"
+#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
+#include "suni.h"
+#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
+#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
+#include "idt77105.h"
+#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
+
+#if BITS_PER_LONG != 32
+#  error FIXME: this driver requires a 32-bit platform
+#endif
+
+/* Additional code ************************************************************/
+
+#include "nicstarmac.c"
+
+
+/* Configurable parameters ****************************************************/
+
+#undef PHY_LOOPBACK
+#undef TX_DEBUG
+#undef RX_DEBUG
+#undef GENERAL_DEBUG
+#undef EXTRA_DEBUG
+
+#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
+                             you're going to use only raw ATM */
+
+
+/* Do not touch these *********************************************************/
+
+#ifdef TX_DEBUG
+#define TXPRINTK(args...) printk(args)
+#else
+#define TXPRINTK(args...)
+#endif /* TX_DEBUG */
+
+#ifdef RX_DEBUG
+#define RXPRINTK(args...) printk(args)
+#else
+#define RXPRINTK(args...)
+#endif /* RX_DEBUG */
+
+#ifdef GENERAL_DEBUG
+#define PRINTK(args...) printk(args)
+#else
+#define PRINTK(args...)
+#endif /* GENERAL_DEBUG */
+
+#ifdef EXTRA_DEBUG
+#define XPRINTK(args...) printk(args)
+#else
+#define XPRINTK(args...)
+#endif /* EXTRA_DEBUG */
+
+
+/* Macros *********************************************************************/
+
+#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
+
+#define NS_DELAY mdelay(1)
+
+#define ALIGN_BUS_ADDR(addr, alignment) \
+        ((((u32) (addr)) + (((u32) (alignment)) - 1)) & ~(((u32) (alignment)) - 1))
+#define ALIGN_ADDRESS(addr, alignment) \
+        bus_to_virt(ALIGN_BUS_ADDR(virt_to_bus(addr), alignment))
+
+#undef CEIL
+
+#ifndef ATM_SKB
+#define ATM_SKB(s) (&(s)->atm)
+#endif
+
+   /* Spinlock debugging stuff */
+#ifdef NS_DEBUG_SPINLOCKS /* See nicstar.h */
+#define ns_grab_int_lock(card,flags) \
+ do { \
+    unsigned long nsdsf, nsdsf2; \
+    local_irq_save(flags); \
+    save_flags(nsdsf); cli();\
+    if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
+                                (flags)&(1<<9)?"en":"dis"); \
+    if (spin_is_locked(&(card)->int_lock) && \
+        (card)->cpu_int == smp_processor_id()) { \
+       printk("nicstar.c: line %d (cpu %d) int_lock already locked at line %d (cpu %d)\n", \
+              __LINE__, smp_processor_id(), (card)->has_int_lock, \
+              (card)->cpu_int); \
+       printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
+    } \
+    if (spin_is_locked(&(card)->res_lock) && \
+        (card)->cpu_res == smp_processor_id()) { \
+       printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying int)\n", \
+              __LINE__, smp_processor_id(), (card)->has_res_lock, \
+              (card)->cpu_res); \
+       printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
+    } \
+    spin_lock_irq(&(card)->int_lock); \
+    (card)->has_int_lock = __LINE__; \
+    (card)->cpu_int = smp_processor_id(); \
+    restore_flags(nsdsf); } while (0)
+#define ns_grab_res_lock(card,flags) \
+ do { \
+    unsigned long nsdsf, nsdsf2; \
+    local_irq_save(flags); \
+    save_flags(nsdsf); cli();\
+    if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
+                                (flags)&(1<<9)?"en":"dis"); \
+    if (spin_is_locked(&(card)->res_lock) && \
+        (card)->cpu_res == smp_processor_id()) { \
+       printk("nicstar.c: line %d (cpu %d) res_lock already locked at line %d (cpu %d)\n", \
+              __LINE__, smp_processor_id(), (card)->has_res_lock, \
+              (card)->cpu_res); \
+       printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
+    } \
+    spin_lock_irq(&(card)->res_lock); \
+    (card)->has_res_lock = __LINE__; \
+    (card)->cpu_res = smp_processor_id(); \
+    restore_flags(nsdsf); } while (0)
+#define ns_grab_scq_lock(card,scq,flags) \
+ do { \
+    unsigned long nsdsf, nsdsf2; \
+    local_irq_save(flags); \
+    save_flags(nsdsf); cli();\
+    if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
+                                (flags)&(1<<9)?"en":"dis"); \
+    if (spin_is_locked(&(scq)->lock) && \
+        (scq)->cpu_lock == smp_processor_id()) { \
+       printk("nicstar.c: line %d (cpu %d) this scq_lock already locked at line %d (cpu %d)\n", \
+              __LINE__, smp_processor_id(), (scq)->has_lock, \
+              (scq)->cpu_lock); \
+       printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
+    } \
+    if (spin_is_locked(&(card)->res_lock) && \
+        (card)->cpu_res == smp_processor_id()) { \
+       printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying scq)\n", \
+              __LINE__, smp_processor_id(), (card)->has_res_lock, \
+              (card)->cpu_res); \
+       printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
+    } \
+    spin_lock_irq(&(scq)->lock); \
+    (scq)->has_lock = __LINE__; \
+    (scq)->cpu_lock = smp_processor_id(); \
+    restore_flags(nsdsf); } while (0)
+#else /* !NS_DEBUG_SPINLOCKS */
+#define ns_grab_int_lock(card,flags) \
+        spin_lock_irqsave(&(card)->int_lock,(flags))
+#define ns_grab_res_lock(card,flags) \
+        spin_lock_irqsave(&(card)->res_lock,(flags))
+#define ns_grab_scq_lock(card,scq,flags) \
+        spin_lock_irqsave(&(scq)->lock,flags)
+#endif /* NS_DEBUG_SPINLOCKS */
+
+
+/* Function declarations ******************************************************/
+
+static u32 ns_read_sram(ns_dev *card, u32 sram_address);
+static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count);
+static int __devinit ns_init_card(int i, struct pci_dev *pcidev);
+static void __devinit ns_init_card_error(ns_dev *card, int error);
+static scq_info *get_scq(int size, u32 scd);
+static void free_scq(scq_info *scq, struct atm_vcc *vcc);
+static void push_rxbufs(ns_dev *card, u32 type, u32 handle1, u32 addr1,
+                       u32 handle2, u32 addr2);
+static irqreturn_t ns_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
+static int ns_open(struct atm_vcc *vcc);
+static void ns_close(struct atm_vcc *vcc);
+static void fill_tst(ns_dev *card, int n, vc_map *vc);
+static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
+static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd,
+                     struct sk_buff *skb);
+static void process_tsq(ns_dev *card);
+static void drain_scq(ns_dev *card, scq_info *scq, int pos);
+static void process_rsq(ns_dev *card);
+static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe);
+#ifdef NS_USE_DESTRUCTORS
+static void ns_sb_destructor(struct sk_buff *sb);
+static void ns_lb_destructor(struct sk_buff *lb);
+static void ns_hb_destructor(struct sk_buff *hb);
+#endif /* NS_USE_DESTRUCTORS */
+static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb);
+static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count);
+static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb);
+static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb);
+static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb);
+static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page);
+static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);
+static void which_list(ns_dev *card, struct sk_buff *skb);
+static void ns_poll(unsigned long arg);
+static int ns_parse_mac(char *mac, unsigned char *esi);
+static short ns_h2i(char c);
+static void ns_phy_put(struct atm_dev *dev, unsigned char value,
+                       unsigned long addr);
+static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
+
+
+
+/* Global variables ***********************************************************/
+
+static struct ns_dev *cards[NS_MAX_CARDS];
+static unsigned num_cards;
+static struct atmdev_ops atm_ops =
+{
+   .open	= ns_open,
+   .close	= ns_close,
+   .ioctl	= ns_ioctl,
+   .send	= ns_send,
+   .phy_put	= ns_phy_put,
+   .phy_get	= ns_phy_get,
+   .proc_read	= ns_proc_read,
+   .owner	= THIS_MODULE,
+};
+static struct timer_list ns_timer;
+static char *mac[NS_MAX_CARDS];
+module_param_array(mac, charp, NULL, 0);
+MODULE_LICENSE("GPL");
+
+
+/* Functions*******************************************************************/
+
+static int __devinit nicstar_init_one(struct pci_dev *pcidev,
+				      const struct pci_device_id *ent)
+{
+   static int index = -1;
+   unsigned int error;
+
+   index++;
+   cards[index] = NULL;
+
+   error = ns_init_card(index, pcidev);
+   if (error) {
+      cards[index--] = NULL;	/* don't increment index */
+      goto err_out;
+   }
+
+   return 0;
+err_out:
+   return -ENODEV;
+}
+
+
+
+static void __devexit nicstar_remove_one(struct pci_dev *pcidev)
+{
+   int i, j;
+   ns_dev *card = pci_get_drvdata(pcidev);
+   struct sk_buff *hb;
+   struct sk_buff *iovb;
+   struct sk_buff *lb;
+   struct sk_buff *sb;
+   
+   i = card->index;
+
+   if (cards[i] == NULL)
+      return;
+
+   if (card->atmdev->phy && card->atmdev->phy->stop)
+      card->atmdev->phy->stop(card->atmdev);
+
+   /* Stop everything */
+   writel(0x00000000, card->membase + CFG);
+
+   /* De-register device */
+   atm_dev_deregister(card->atmdev);
+
+   /* Disable PCI device */
+   pci_disable_device(pcidev);
+   
+   /* Free up resources */
+   j = 0;
+   PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
+   while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
+   {
+      dev_kfree_skb_any(hb);
+      j++;
+   }
+   PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
+   j = 0;
+   PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, card->iovpool.count);
+   while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
+   {
+      dev_kfree_skb_any(iovb);
+      j++;
+   }
+   PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
+   while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
+      dev_kfree_skb_any(lb);
+   while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
+      dev_kfree_skb_any(sb);
+   free_scq(card->scq0, NULL);
+   for (j = 0; j < NS_FRSCD_NUM; j++)
+   {
+      if (card->scd2vc[j] != NULL)
+         free_scq(card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
+   }
+   kfree(card->rsq.org);
+   kfree(card->tsq.org);
+   free_irq(card->pcidev->irq, card);
+   iounmap(card->membase);
+   kfree(card);
+}
+
+
+
+static struct pci_device_id nicstar_pci_tbl[] __devinitdata =
+{
+	{PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77201,
+	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+	{0,}			/* terminate list */
+};
+MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
+
+
+
+static struct pci_driver nicstar_driver = {
+	.name		= "nicstar",
+	.id_table	= nicstar_pci_tbl,
+	.probe		= nicstar_init_one,
+	.remove		= __devexit_p(nicstar_remove_one),
+};
+
+
+
+static int __init nicstar_init(void)
+{
+   unsigned error = 0;	/* Initialized to remove compile warning */
+
+   XPRINTK("nicstar: nicstar_init() called.\n");
+
+   error = pci_register_driver(&nicstar_driver);
+   
+   TXPRINTK("nicstar: TX debug enabled.\n");
+   RXPRINTK("nicstar: RX debug enabled.\n");
+   PRINTK("nicstar: General debug enabled.\n");
+#ifdef PHY_LOOPBACK
+   printk("nicstar: using PHY loopback.\n");
+#endif /* PHY_LOOPBACK */
+   XPRINTK("nicstar: nicstar_init() returned.\n");
+
+   if (!error) {
+      init_timer(&ns_timer);
+      ns_timer.expires = jiffies + NS_POLL_PERIOD;
+      ns_timer.data = 0UL;
+      ns_timer.function = ns_poll;
+      add_timer(&ns_timer);
+   }
+   
+   return error;
+}
+
+
+
+static void __exit nicstar_cleanup(void)
+{
+   XPRINTK("nicstar: nicstar_cleanup() called.\n");
+
+   del_timer(&ns_timer);
+
+   pci_unregister_driver(&nicstar_driver);
+
+   XPRINTK("nicstar: nicstar_cleanup() returned.\n");
+}
+
+
+
+static u32 ns_read_sram(ns_dev *card, u32 sram_address)
+{
+   unsigned long flags;
+   u32 data;
+   sram_address <<= 2;
+   sram_address &= 0x0007FFFC;	/* address must be dword aligned */
+   sram_address |= 0x50000000;	/* SRAM read command */
+   ns_grab_res_lock(card, flags);
+   while (CMD_BUSY(card));
+   writel(sram_address, card->membase + CMD);
+   while (CMD_BUSY(card));
+   data = readl(card->membase + DR0);
+   spin_unlock_irqrestore(&card->res_lock, flags);
+   return data;
+}
+
+
+   
+static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count)
+{
+   unsigned long flags;
+   int i, c;
+   count--;	/* count range now is 0..3 instead of 1..4 */
+   c = count;
+   c <<= 2;	/* to use increments of 4 */
+   ns_grab_res_lock(card, flags);
+   while (CMD_BUSY(card));
+   for (i = 0; i <= c; i += 4)
+      writel(*(value++), card->membase + i);
+   /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
+            so card->membase + DR0 == card->membase */
+   sram_address <<= 2;
+   sram_address &= 0x0007FFFC;
+   sram_address |= (0x40000000 | count);
+   writel(sram_address, card->membase + CMD);
+   spin_unlock_irqrestore(&card->res_lock, flags);
+}
+
+
+static int __devinit ns_init_card(int i, struct pci_dev *pcidev)
+{
+   int j;
+   struct ns_dev *card = NULL;
+   unsigned char pci_latency;
+   unsigned error;
+   u32 data;
+   u32 u32d[4];
+   u32 ns_cfg_rctsize;
+   int bcount;
+   unsigned long membase;
+
+   error = 0;
+
+   if (pci_enable_device(pcidev))
+   {
+      printk("nicstar%d: can't enable PCI device\n", i);
+      error = 2;
+      ns_init_card_error(card, error);
+      return error;
+   }
+
+   if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL)
+   {
+      printk("nicstar%d: can't allocate memory for device structure.\n", i);
+      error = 2;
+      ns_init_card_error(card, error);
+      return error;
+   }
+   cards[i] = card;
+   spin_lock_init(&card->int_lock);
+   spin_lock_init(&card->res_lock);
+      
+   pci_set_drvdata(pcidev, card);
+   
+   card->index = i;
+   card->atmdev = NULL;
+   card->pcidev = pcidev;
+   membase = pci_resource_start(pcidev, 1);
+   card->membase = ioremap(membase, NS_IOREMAP_SIZE);
+   if (card->membase == 0)
+   {
+      printk("nicstar%d: can't ioremap() membase.\n",i);
+      error = 3;
+      ns_init_card_error(card, error);
+      return error;
+   }
+   PRINTK("nicstar%d: membase at 0x%x.\n", i, card->membase);
+
+   pci_set_master(pcidev);
+
+   if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0)
+   {
+      printk("nicstar%d: can't read PCI latency timer.\n", i);
+      error = 6;
+      ns_init_card_error(card, error);
+      return error;
+   }
+#ifdef NS_PCI_LATENCY
+   if (pci_latency < NS_PCI_LATENCY)
+   {
+      PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, NS_PCI_LATENCY);
+      for (j = 1; j < 4; j++)
+      {
+         if (pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
+	    break;
+      }
+      if (j == 4)
+      {
+         printk("nicstar%d: can't set PCI latency timer to %d.\n", i, NS_PCI_LATENCY);
+         error = 7;
+         ns_init_card_error(card, error);
+	 return error;
+      }
+   }
+#endif /* NS_PCI_LATENCY */
+      
+   /* Clear timer overflow */
+   data = readl(card->membase + STAT);
+   if (data & NS_STAT_TMROF)
+      writel(NS_STAT_TMROF, card->membase + STAT);
+
+   /* Software reset */
+   writel(NS_CFG_SWRST, card->membase + CFG);
+   NS_DELAY;
+   writel(0x00000000, card->membase + CFG);
+
+   /* PHY reset */
+   writel(0x00000008, card->membase + GP);
+   NS_DELAY;
+   writel(0x00000001, card->membase + GP);
+   NS_DELAY;
+   while (CMD_BUSY(card));
+   writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD);	/* Sync UTOPIA with SAR clock */
+   NS_DELAY;
+      
+   /* Detect PHY type */
+   while (CMD_BUSY(card));
+   writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
+   while (CMD_BUSY(card));
+   data = readl(card->membase + DR0);
+   switch(data) {
+      case 0x00000009:
+         printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
+         card->max_pcr = ATM_25_PCR;
+         while(CMD_BUSY(card));
+         writel(0x00000008, card->membase + DR0);
+         writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
+         /* Clear an eventual pending interrupt */
+         writel(NS_STAT_SFBQF, card->membase + STAT);
+#ifdef PHY_LOOPBACK
+         while(CMD_BUSY(card));
+         writel(0x00000022, card->membase + DR0);
+         writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
+#endif /* PHY_LOOPBACK */
+	 break;
+      case 0x00000030:
+      case 0x00000031:
+         printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
+         card->max_pcr = ATM_OC3_PCR;
+#ifdef PHY_LOOPBACK
+         while(CMD_BUSY(card));
+         writel(0x00000002, card->membase + DR0);
+         writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
+#endif /* PHY_LOOPBACK */
+	 break;
+      default:
+         printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
+         error = 8;
+         ns_init_card_error(card, error);
+         return error;
+   }
+   writel(0x00000000, card->membase + GP);
+
+   /* Determine SRAM size */
+   data = 0x76543210;
+   ns_write_sram(card, 0x1C003, &data, 1);
+   data = 0x89ABCDEF;
+   ns_write_sram(card, 0x14003, &data, 1);
+   if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
+       ns_read_sram(card, 0x1C003) == 0x76543210)
+       card->sram_size = 128;
+   else
+      card->sram_size = 32;
+   PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
+
+   card->rct_size = NS_MAX_RCTSIZE;
+
+#if (NS_MAX_RCTSIZE == 4096)
+   if (card->sram_size == 128)
+      printk("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", i);
+#elif (NS_MAX_RCTSIZE == 16384)
+   if (card->sram_size == 32)
+   {
+      printk("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", i);
+      card->rct_size = 4096;
+   }
+#else
+#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
+#endif
+
+   card->vpibits = NS_VPIBITS;
+   if (card->rct_size == 4096)
+      card->vcibits = 12 - NS_VPIBITS;
+   else /* card->rct_size == 16384 */
+      card->vcibits = 14 - NS_VPIBITS;
+
+   /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
+   if (mac[i] == NULL)
+      nicstar_init_eprom(card->membase);
+
+   if (request_irq(pcidev->irq, &ns_irq_handler, SA_INTERRUPT | SA_SHIRQ, "nicstar", card) != 0)
+   {
+      printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
+      error = 9;
+      ns_init_card_error(card, error);
+      return error;
+   }
+
+   /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
+   writel(0x00000000, card->membase + VPM);
+      
+   /* Initialize TSQ */
+   card->tsq.org = kmalloc(NS_TSQSIZE + NS_TSQ_ALIGNMENT, GFP_KERNEL);
+   if (card->tsq.org == NULL)
+   {
+      printk("nicstar%d: can't allocate TSQ.\n", i);
+      error = 10;
+      ns_init_card_error(card, error);
+      return error;
+   }
+   card->tsq.base = (ns_tsi *) ALIGN_ADDRESS(card->tsq.org, NS_TSQ_ALIGNMENT);
+   card->tsq.next = card->tsq.base;
+   card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
+   for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
+      ns_tsi_init(card->tsq.base + j);
+   writel(0x00000000, card->membase + TSQH);
+   writel((u32) virt_to_bus(card->tsq.base), card->membase + TSQB);
+   PRINTK("nicstar%d: TSQ base at 0x%x  0x%x  0x%x.\n", i, (u32) card->tsq.base,
+          (u32) virt_to_bus(card->tsq.base), readl(card->membase + TSQB));
+      
+   /* Initialize RSQ */
+   card->rsq.org = kmalloc(NS_RSQSIZE + NS_RSQ_ALIGNMENT, GFP_KERNEL);
+   if (card->rsq.org == NULL)
+   {
+      printk("nicstar%d: can't allocate RSQ.\n", i);
+      error = 11;
+      ns_init_card_error(card, error);
+      return error;
+   }
+   card->rsq.base = (ns_rsqe *) ALIGN_ADDRESS(card->rsq.org, NS_RSQ_ALIGNMENT);
+   card->rsq.next = card->rsq.base;
+   card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
+   for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
+      ns_rsqe_init(card->rsq.base + j);
+   writel(0x00000000, card->membase + RSQH);
+   writel((u32) virt_to_bus(card->rsq.base), card->membase + RSQB);
+   PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base);
+      
+   /* Initialize SCQ0, the only VBR SCQ used */
+   card->scq1 = (scq_info *) NULL;
+   card->scq2 = (scq_info *) NULL;
+   card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0);
+   if (card->scq0 == (scq_info *) NULL)
+   {
+      printk("nicstar%d: can't get SCQ0.\n", i);
+      error = 12;
+      ns_init_card_error(card, error);
+      return error;
+   }
+   u32d[0] = (u32) virt_to_bus(card->scq0->base);
+   u32d[1] = (u32) 0x00000000;
+   u32d[2] = (u32) 0xffffffff;
+   u32d[3] = (u32) 0x00000000;
+   ns_write_sram(card, NS_VRSCD0, u32d, 4);
+   ns_write_sram(card, NS_VRSCD1, u32d, 4);	/* These last two won't be used */
+   ns_write_sram(card, NS_VRSCD2, u32d, 4);	/* but are initialized, just in case... */
+   card->scq0->scd = NS_VRSCD0;
+   PRINTK("nicstar%d: VBR-SCQ0 base at 0x%x.\n", i, (u32) card->scq0->base);
+
+   /* Initialize TSTs */
+   card->tst_addr = NS_TST0;
+   card->tst_free_entries = NS_TST_NUM_ENTRIES;
+   data = NS_TST_OPCODE_VARIABLE;
+   for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
+      ns_write_sram(card, NS_TST0 + j, &data, 1);
+   data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
+   ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
+   for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
+      ns_write_sram(card, NS_TST1 + j, &data, 1);
+   data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
+   ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
+   for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
+      card->tste2vc[j] = NULL;
+   writel(NS_TST0 << 2, card->membase + TSTB);
+
+
+   /* Initialize RCT. AAL type is set on opening the VC. */
+#ifdef RCQ_SUPPORT
+   u32d[0] = NS_RCTE_RAWCELLINTEN;
+#else
+   u32d[0] = 0x00000000;
+#endif /* RCQ_SUPPORT */
+   u32d[1] = 0x00000000;
+   u32d[2] = 0x00000000;
+   u32d[3] = 0xFFFFFFFF;
+   for (j = 0; j < card->rct_size; j++)
+      ns_write_sram(card, j * 4, u32d, 4);      
+      
+   memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
+      
+   for (j = 0; j < NS_FRSCD_NUM; j++)
+      card->scd2vc[j] = NULL;
+
+   /* Initialize buffer levels */
+   card->sbnr.min = MIN_SB;
+   card->sbnr.init = NUM_SB;
+   card->sbnr.max = MAX_SB;
+   card->lbnr.min = MIN_LB;
+   card->lbnr.init = NUM_LB;
+   card->lbnr.max = MAX_LB;
+   card->iovnr.min = MIN_IOVB;
+   card->iovnr.init = NUM_IOVB;
+   card->iovnr.max = MAX_IOVB;
+   card->hbnr.min = MIN_HB;
+   card->hbnr.init = NUM_HB;
+   card->hbnr.max = MAX_HB;
+   
+   card->sm_handle = 0x00000000;
+   card->sm_addr = 0x00000000;
+   card->lg_handle = 0x00000000;
+   card->lg_addr = 0x00000000;
+   
+   card->efbie = 1;	/* To prevent push_rxbufs from enabling the interrupt */
+
+   /* Pre-allocate some huge buffers */
+   skb_queue_head_init(&card->hbpool.queue);
+   card->hbpool.count = 0;
+   for (j = 0; j < NUM_HB; j++)
+   {
+      struct sk_buff *hb;
+      hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
+      if (hb == NULL)
+      {
+         printk("nicstar%d: can't allocate %dth of %d huge buffers.\n",
+                i, j, NUM_HB);
+         error = 13;
+         ns_init_card_error(card, error);
+	 return error;
+      }
+      skb_queue_tail(&card->hbpool.queue, hb);
+      card->hbpool.count++;
+   }
+
+
+   /* Allocate large buffers */
+   skb_queue_head_init(&card->lbpool.queue);
+   card->lbpool.count = 0;			/* Not used */
+   for (j = 0; j < NUM_LB; j++)
+   {
+      struct sk_buff *lb;
+      lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
+      if (lb == NULL)
+      {
+         printk("nicstar%d: can't allocate %dth of %d large buffers.\n",
+                i, j, NUM_LB);
+         error = 14;
+         ns_init_card_error(card, error);
+	 return error;
+      }
+      skb_queue_tail(&card->lbpool.queue, lb);
+      skb_reserve(lb, NS_SMBUFSIZE);
+      push_rxbufs(card, BUF_LG, (u32) lb, (u32) virt_to_bus(lb->data), 0, 0);
+      /* Due to the implementation of push_rxbufs() this is 1, not 0 */
+      if (j == 1)
+      {
+         card->rcbuf = lb;
+         card->rawch = (u32) virt_to_bus(lb->data);
+      }
+   }
+   /* Test for strange behaviour which leads to crashes */
+   if ((bcount = ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min)
+   {
+      printk("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
+             i, j, bcount);
+      error = 14;
+      ns_init_card_error(card, error);
+      return error;
+   }
+      
+
+   /* Allocate small buffers */
+   skb_queue_head_init(&card->sbpool.queue);
+   card->sbpool.count = 0;			/* Not used */
+   for (j = 0; j < NUM_SB; j++)
+   {
+      struct sk_buff *sb;
+      sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
+      if (sb == NULL)
+      {
+         printk("nicstar%d: can't allocate %dth of %d small buffers.\n",
+                i, j, NUM_SB);
+         error = 15;
+         ns_init_card_error(card, error);
+	 return error;
+      }
+      skb_queue_tail(&card->sbpool.queue, sb);
+      skb_reserve(sb, NS_AAL0_HEADER);
+      push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data), 0, 0);
+   }
+   /* Test for strange behaviour which leads to crashes */
+   if ((bcount = ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min)
+   {
+      printk("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
+             i, j, bcount);
+      error = 15;
+      ns_init_card_error(card, error);
+      return error;
+   }
+      
+
+   /* Allocate iovec buffers */
+   skb_queue_head_init(&card->iovpool.queue);
+   card->iovpool.count = 0;
+   for (j = 0; j < NUM_IOVB; j++)
+   {
+      struct sk_buff *iovb;
+      iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
+      if (iovb == NULL)
+      {
+         printk("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
+                i, j, NUM_IOVB);
+         error = 16;
+         ns_init_card_error(card, error);
+	 return error;
+      }
+      skb_queue_tail(&card->iovpool.queue, iovb);
+      card->iovpool.count++;
+   }
+
+   card->intcnt = 0;
+
+   /* Configure NICStAR */
+   if (card->rct_size == 4096)
+      ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
+   else /* (card->rct_size == 16384) */
+      ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
+
+   card->efbie = 1;
+
+   /* Register device */
+   card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL);
+   if (card->atmdev == NULL)
+   {
+      printk("nicstar%d: can't register device.\n", i);
+      error = 17;
+      ns_init_card_error(card, error);
+      return error;
+   }
+      
+   if (ns_parse_mac(mac[i], card->atmdev->esi)) {
+      nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
+                         card->atmdev->esi, 6);
+      if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) == 0) {
+         nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
+                         card->atmdev->esi, 6);
+      }
+   }
+
+   printk("nicstar%d: MAC address %02X:%02X:%02X:%02X:%02X:%02X\n", i,
+          card->atmdev->esi[0], card->atmdev->esi[1], card->atmdev->esi[2],
+          card->atmdev->esi[3], card->atmdev->esi[4], card->atmdev->esi[5]);
+
+   card->atmdev->dev_data = card;
+   card->atmdev->ci_range.vpi_bits = card->vpibits;
+   card->atmdev->ci_range.vci_bits = card->vcibits;
+   card->atmdev->link_rate = card->max_pcr;
+   card->atmdev->phy = NULL;
+
+#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
+   if (card->max_pcr == ATM_OC3_PCR)
+      suni_init(card->atmdev);
+#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
+
+#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
+   if (card->max_pcr == ATM_25_PCR)
+      idt77105_init(card->atmdev);
+#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
+
+   if (card->atmdev->phy && card->atmdev->phy->start)
+      card->atmdev->phy->start(card->atmdev);
+
+   writel(NS_CFG_RXPATH |
+          NS_CFG_SMBUFSIZE |
+          NS_CFG_LGBUFSIZE |
+          NS_CFG_EFBIE |
+          NS_CFG_RSQSIZE |
+          NS_CFG_VPIBITS |
+          ns_cfg_rctsize |
+          NS_CFG_RXINT_NODELAY |
+          NS_CFG_RAWIE |		/* Only enabled if RCQ_SUPPORT */
+          NS_CFG_RSQAFIE |
+          NS_CFG_TXEN |
+          NS_CFG_TXIE |
+          NS_CFG_TSQFIE_OPT |		/* Only enabled if ENABLE_TSQFIE */ 
+          NS_CFG_PHYIE,
+          card->membase + CFG);
+
+   num_cards++;
+
+   return error;
+}
+
+
+
+static void __devinit ns_init_card_error(ns_dev *card, int error)
+{
+   if (error >= 17)
+   {
+      writel(0x00000000, card->membase + CFG);
+   }
+   if (error >= 16)
+   {
+      struct sk_buff *iovb;
+      while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
+         dev_kfree_skb_any(iovb);
+   }
+   if (error >= 15)
+   {
+      struct sk_buff *sb;
+      while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
+         dev_kfree_skb_any(sb);
+      free_scq(card->scq0, NULL);
+   }
+   if (error >= 14)
+   {
+      struct sk_buff *lb;
+      while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
+         dev_kfree_skb_any(lb);
+   }
+   if (error >= 13)
+   {
+      struct sk_buff *hb;
+      while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
+         dev_kfree_skb_any(hb);
+   }
+   if (error >= 12)
+   {
+      kfree(card->rsq.org);
+   }
+   if (error >= 11)
+   {
+      kfree(card->tsq.org);
+   }
+   if (error >= 10)
+   {
+      free_irq(card->pcidev->irq, card);
+   }
+   if (error >= 4)
+   {
+      iounmap(card->membase);
+   }
+   if (error >= 3)
+   {
+      pci_disable_device(card->pcidev);
+      kfree(card);
+   }
+}
+
+
+
+static scq_info *get_scq(int size, u32 scd)
+{
+   scq_info *scq;
+   int i;
+
+   if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
+      return (scq_info *) NULL;
+
+   scq = (scq_info *) kmalloc(sizeof(scq_info), GFP_KERNEL);
+   if (scq == (scq_info *) NULL)
+      return (scq_info *) NULL;
+   scq->org = kmalloc(2 * size, GFP_KERNEL);
+   if (scq->org == NULL)
+   {
+      kfree(scq);
+      return (scq_info *) NULL;
+   }
+   scq->skb = (struct sk_buff **) kmalloc(sizeof(struct sk_buff *) *
+                                          (size / NS_SCQE_SIZE), GFP_KERNEL);
+   if (scq->skb == (struct sk_buff **) NULL)
+   {
+      kfree(scq->org);
+      kfree(scq);
+      return (scq_info *) NULL;
+   }
+   scq->num_entries = size / NS_SCQE_SIZE;
+   scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size);
+   scq->next = scq->base;
+   scq->last = scq->base + (scq->num_entries - 1);
+   scq->tail = scq->last;
+   scq->scd = scd;
+   scq->num_entries = size / NS_SCQE_SIZE;
+   scq->tbd_count = 0;
+   init_waitqueue_head(&scq->scqfull_waitq);
+   scq->full = 0;
+   spin_lock_init(&scq->lock);
+
+   for (i = 0; i < scq->num_entries; i++)
+      scq->skb[i] = NULL;
+
+   return scq;
+}
+
+
+
+/* For variable rate SCQ vcc must be NULL */
+static void free_scq(scq_info *scq, struct atm_vcc *vcc)
+{
+   int i;
+
+   if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
+      for (i = 0; i < scq->num_entries; i++)
+      {
+         if (scq->skb[i] != NULL)
+	 {
+            vcc = ATM_SKB(scq->skb[i])->vcc;
+            if (vcc->pop != NULL)
+	       vcc->pop(vcc, scq->skb[i]);
+	    else
+               dev_kfree_skb_any(scq->skb[i]);
+         }
+      }
+   else /* vcc must be != NULL */
+   {
+      if (vcc == NULL)
+      {
+         printk("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
+         for (i = 0; i < scq->num_entries; i++)
+            dev_kfree_skb_any(scq->skb[i]);
+      }
+      else
+         for (i = 0; i < scq->num_entries; i++)
+         {