diff options
| author | Will Deacon <will.deacon@arm.com> | 2011-08-03 12:37:04 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-08-12 15:41:15 +0100 |
| commit | 72dc53acd50db066a5a5ebe1f39fae73d7e62aa8 (patch) | |
| tree | cbdc3bdbd0802992d6f4db26ffa4a5a61354226d /arch | |
| parent | dfc40b24c0a37593724f3317cd485c73ee878c18 (diff) | |
ARM: cache: detect VIPT aliasing I-cache on ARMv6
The current cache detection code does not check for an aliasing
I-cache if the D-cache is found to be VIPT aliasing.
This patch fixes the problem by always checking for an aliasing
I-cache on v6 and later.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/kernel/setup.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 70bca649e92..e514c76043b 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -280,18 +280,19 @@ static void __init cacheid_init(void) if (arch >= CPU_ARCH_ARMv6) { if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ + arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING; if ((cachetype & (3 << 14)) == 1 << 14) cacheid |= CACHEID_ASID_TAGGED; - else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7)) - cacheid |= CACHEID_VIPT_I_ALIASING; - } else if (cachetype & (1 << 23)) { - cacheid = CACHEID_VIPT_ALIASING; } else { - cacheid = CACHEID_VIPT_NONALIASING; - if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6)) - cacheid |= CACHEID_VIPT_I_ALIASING; + arch = CPU_ARCH_ARMv6; + if (cachetype & (1 << 23)) + cacheid = CACHEID_VIPT_ALIASING; + else + cacheid = CACHEID_VIPT_NONALIASING; } + if (cpu_has_aliasing_icache(arch)) + cacheid |= CACHEID_VIPT_I_ALIASING; } else { cacheid = CACHEID_VIVT; } |