diff options
author | David S. Miller <davem@davemloft.net> | 2010-01-04 23:16:03 -0800 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-01-22 15:18:33 -0800 |
commit | 4bff5fff57875872c813022bfa3a523b88196c98 (patch) | |
tree | fdc6fd8fefe84ab6de0e4651bfe37b28712417f5 /arch | |
parent | 9d6567c5369d439440ad96e8b402919d4480e2c6 (diff) |
sparc64: Fix Niagara2 perf event handling.
[ Upstream commit e04ed38d4e0cd32141f723560efcc8252b0241e2 ]
For chips like Niagara2 that have true overflow indications
in the %pcr (which we don't actually need and don't use)
the interrupt signal persists until the overflow bits are
cleared by an explicit %pcr write.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sparc/kernel/perf_event.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index fa5936e1c3b..198fb4e79ba 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self, data.addr = 0; cpuc = &__get_cpu_var(cpu_hw_events); + + /* If the PMU has the TOE IRQ enable bits, we need to do a + * dummy write to the %pcr to clear the overflow bits and thus + * the interrupt. + * + * Do this before we peek at the counters to determine + * overflow so we don't lose any events. + */ + if (sparc_pmu->irq_bit) + pcr_ops->write(cpuc->pcr); + for (idx = 0; idx < MAX_HWEVENTS; idx++) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc; |