ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock

This patch changes prefix of the clk register from S5P_ to
EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix
exynos4_ on clk declarations.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

7 files changed, 766 insertions, 762 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 860b73fcd2a..31b59e65463 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * EXYNOS4 - Clock support
@@ -31,85 +31,85 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4_clock_save[] = {
-	SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-	SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-	SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-	SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-	SAVE_ITEM(S5P_CLKSRC_TOP0),
-	SAVE_ITEM(S5P_CLKSRC_TOP1),
-	SAVE_ITEM(S5P_CLKSRC_CAM),
-	SAVE_ITEM(S5P_CLKSRC_TV),
-	SAVE_ITEM(S5P_CLKSRC_MFC),
-	SAVE_ITEM(S5P_CLKSRC_G3D),
-	SAVE_ITEM(S5P_CLKSRC_LCD0),
-	SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-	SAVE_ITEM(S5P_CLKSRC_FSYS),
-	SAVE_ITEM(S5P_CLKSRC_PERIL0),
-	SAVE_ITEM(S5P_CLKSRC_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV_CAM),
-	SAVE_ITEM(S5P_CLKDIV_TV),
-	SAVE_ITEM(S5P_CLKDIV_MFC),
-	SAVE_ITEM(S5P_CLKDIV_G3D),
-	SAVE_ITEM(S5P_CLKDIV_LCD0),
-	SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-	SAVE_ITEM(S5P_CLKDIV_FSYS0),
-	SAVE_ITEM(S5P_CLKDIV_FSYS1),
-	SAVE_ITEM(S5P_CLKDIV_FSYS2),
-	SAVE_ITEM(S5P_CLKDIV_FSYS3),
-	SAVE_ITEM(S5P_CLKDIV_PERIL0),
-	SAVE_ITEM(S5P_CLKDIV_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV_PERIL2),
-	SAVE_ITEM(S5P_CLKDIV_PERIL3),
-	SAVE_ITEM(S5P_CLKDIV_PERIL4),
-	SAVE_ITEM(S5P_CLKDIV_PERIL5),
-	SAVE_ITEM(S5P_CLKDIV_TOP),
-	SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-	SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-	SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-	SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-	SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-	SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-	SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-	SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV2_RATIO),
-	SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-	SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-	SAVE_ITEM(S5P_CLKGATE_IP_TV),
-	SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-	SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-	SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-	SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-	SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-	SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-	SAVE_ITEM(S5P_CLKGATE_BLOCK),
-	SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-	SAVE_ITEM(S5P_CLKSRC_DMC),
-	SAVE_ITEM(S5P_CLKDIV_DMC0),
-	SAVE_ITEM(S5P_CLKDIV_DMC1),
-	SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-	SAVE_ITEM(S5P_CLKSRC_CPU),
-	SAVE_ITEM(S5P_CLKDIV_CPU),
-	SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-	SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-	SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+	SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
 };
 #endif
 
-static struct clk clk_sclk_hdmi27m = {
+static struct clk exynos4_clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.rate		= 27000000,
 };
 
-static struct clk clk_sclk_hdmiphy = {
+static struct clk exynos4_clk_sclk_hdmiphy = {
 	.name		= "sclk_hdmiphy",
 };
 
-static struct clk clk_sclk_usbphy0 = {
+static struct clk exynos4_clk_sclk_usbphy0 = {
 	.name		= "sclk_usbphy0",
 	.rate		= 27000000,
 };
 
-static struct clk clk_sclk_usbphy1 = {
+static struct clk exynos4_clk_sclk_usbphy1 = {
 	.name		= "sclk_usbphy1",
 };
 
@@ -120,82 +120,82 @@ static struct clk dummy_apb_pclk = {
 
 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 }
 
 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 }
 
 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 }
 
 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 }
 
 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 }
 
 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 }
 
 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 }
 
 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 }
 
 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 }
 
 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 }
 
 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 }
 
 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 }
 
 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+	return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 }
 
 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 }
 
 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 }
 
 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
@@ -210,31 +210,31 @@ static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 
 /* Core list of CMU_CPU side */
 
-static struct clksrc_clk clk_mout_apll = {
+static struct clksrc_clk exynos4_clk_mout_apll = {
 	.clk	= {
 		.name		= "mout_apll",
 	},
 	.sources = &clk_src_apll,
-	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_apll = {
+static struct clksrc_clk exynos4_clk_sclk_apll = {
 	.clk	= {
 		.name		= "sclk_apll",
-		.parent		= &clk_mout_apll.clk,
+		.parent		= &exynos4_clk_mout_apll.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
-static struct clksrc_clk clk_mout_epll = {
+static struct clksrc_clk exynos4_clk_mout_epll = {
 	.clk	= {
 		.name		= "mout_epll",
 	},
 	.sources = &clk_src_epll,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
 
-struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk exynos4_clk_mout_mpll = {
 	.clk	= {
 		.name		= "mout_mpll",
 	},
@@ -243,221 +243,221 @@ struct clksrc_clk clk_mout_mpll = {
 	/* reg_src will be added in each SoCs' clock */
 };
 
-static struct clk *clkset_moutcore_list[] = {
-	[0] = &clk_mout_apll.clk,
-	[1] = &clk_mout_mpll.clk,
+static struct clk *exynos4_clkset_moutcore_list[] = {
+	[0] = &exynos4_clk_mout_apll.clk,
+	[1] = &exynos4_clk_mout_mpll.clk,
 };
 
-static struct clksrc_sources clkset_moutcore = {
-	.sources	= clkset_moutcore_list,
-	.nr_sources	= ARRAY_SIZE(clkset_moutcore_list),
+static struct clksrc_sources exynos4_clkset_moutcore = {
+	.sources	= exynos4_clkset_moutcore_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_moutcore_list),
 };
 
-static struct clksrc_clk clk_moutcore = {
+static struct clksrc_clk exynos4_clk_moutcore = {
 	.clk	= {
 		.name		= "moutcore",
 	},
-	.sources = &clkset_moutcore,
-	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+	.sources = &exynos4_clkset_moutcore,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 };
 
-static struct clksrc_clk clk_coreclk = {
+static struct clksrc_clk exynos4_clk_coreclk = {
 	.clk	= {
 		.name		= "core_clk",
-		.parent		= &clk_moutcore.clk,
+		.parent		= &exynos4_clk_moutcore.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_armclk = {
+static struct clksrc_clk exynos4_clk_armclk = {
 	.clk	= {
 		.name		= "armclk",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
 };
 
-static struct clksrc_clk clk_aclk_corem0 = {
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 	.clk	= {
 		.name		= "aclk_corem0",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_cores = {
+static struct clksrc_clk exynos4_clk_aclk_cores = {
 	.clk	= {
 		.name		= "aclk_cores",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_corem1 = {
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 	.clk	= {
 		.name		= "aclk_corem1",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 };
 
-static struct clksrc_clk clk_periphclk = {
+static struct clksrc_clk exynos4_clk_periphclk = {
 	.clk	= {
 		.name		= "periphclk",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 };
 
 /* Core list of CMU_CORE side */
 
-static struct clk *clkset_corebus_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_corebus_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-struct clksrc_sources clkset_mout_corebus = {
-	.sources	= clkset_corebus_list,
-	.nr_sources	= ARRAY_SIZE(clkset_corebus_list),
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+	.sources	= exynos4_clkset_corebus_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_corebus_list),
 };
 
-static struct clksrc_clk clk_mout_corebus = {
+static struct clksrc_clk exynos4_clk_mout_corebus = {
 	.clk	= {
 		.name		= "mout_corebus",
 	},
-	.sources = &clkset_mout_corebus,
-	.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_corebus,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_dmc = {
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
 	.clk	= {
 		.name		= "sclk_dmc",
-		.parent		= &clk_mout_corebus.clk,
+		.parent		= &exynos4_clk_mout_corebus.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_cored = {
+static struct clksrc_clk exynos4_clk_aclk_cored = {
 	.clk	= {
 		.name		= "aclk_cored",
-		.parent		= &clk_sclk_dmc.clk,
+		.parent		= &exynos4_clk_sclk_dmc.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_corep = {
+static struct clksrc_clk exynos4_clk_aclk_corep = {
 	.clk	= {
 		.name		= "aclk_corep",
-		.parent		= &clk_aclk_cored.clk,
+		.parent		= &exynos4_clk_aclk_cored.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_acp = {
+static struct clksrc_clk exynos4_clk_aclk_acp = {
 	.clk	= {
 		.name		= "aclk_acp",
-		.parent		= &clk_mout_corebus.clk,
+		.parent		= &exynos4_clk_mout_corebus.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_pclk_acp = {
+static struct clksrc_clk exynos4_clk_pclk_acp = {
 	.clk	= {
 		.name		= "pclk_acp",
-		.parent		= &clk_aclk_acp.clk,
+		.parent		= &exynos4_clk_aclk_acp.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 };
 
 /* Core list of CMU_TOP side */
 
-struct clk *clkset_aclk_top_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+struct clk *exynos4_clkset_aclk_top_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_aclk = {
-	.sources	= clkset_aclk_top_list,
-	.nr_sources	= ARRAY_SIZE(clkset_aclk_top_list),
+static struct clksrc_sources exynos4_clkset_aclk = {
+	.sources	= exynos4_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 };
 
-static struct clksrc_clk clk_aclk_200 = {
+static struct clksrc_clk exynos4_clk_aclk_200 = {
 	.clk	= {
 		.name		= "aclk_200",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_100 = {
+static struct clksrc_clk exynos4_clk_aclk_100 = {
 	.clk	= {
 		.name		= "aclk_100",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 };
 
-static struct clksrc_clk clk_aclk_160 = {
+static struct clksrc_clk exynos4_clk_aclk_160 = {
 	.clk	= {
 		.name		= "aclk_160",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
-struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk exynos4_clk_aclk_133 = {
 	.clk	= {
 		.name		= "aclk_133",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 };
 
-static struct clk *clkset_vpllsrc_list[] = {
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
 	[0] = &clk_fin_vpll,
-	[1] = &clk_sclk_hdmi27m,
+	[1] = &exynos4_clk_sclk_hdmi27m,
 };
 
-static struct clksrc_sources clkset_vpllsrc = {
-	.sources	= clkset_vpllsrc_list,
-	.nr_sources	= ARRAY_SIZE(clkset_vpllsrc_list),
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+	.sources	= exynos4_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 };
 
-static struct clksrc_clk clk_vpllsrc = {
+static struct clksrc_clk exynos4_clk_vpllsrc = {
 	.clk	= {
 		.name		= "vpll_src",
 		.enable		= exynos4_clksrc_mask_top_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources = &clkset_vpllsrc,
-	.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_sclk_vpll_list[] = {
-	[0] = &clk_vpllsrc.clk,
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+	[0] = &exynos4_clk_vpllsrc.clk,
 	[1] = &clk_fout_vpll,
 };
 
-static struct clksrc_sources clkset_sclk_vpll = {
-	.sources	= clkset_sclk_vpll_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_vpll_list),
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+	.sources	= exynos4_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 };
 
-static struct clksrc_clk clk_sclk_vpll = {
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
 	.clk	= {
 		.name		= "sclk_vpll",
 	},
-	.sources = &clkset_sclk_vpll,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.sources = &exynos4_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
-static struct clk init_clocks_off[] = {
+static struct clk exynos4_init_clocks_off[] = {
 	{
 		.name		= "timers",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1<<24),
 	}, {
@@ -498,30 +498,30 @@ static struct clk init_clocks_off[] = {
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.0",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.1",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.2",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.3",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
 		.name		= "dwmmc",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
@@ -568,7 +568,7 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 15),
 	}, {
 		.name		= "watchdog",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_perir_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
@@ -626,55 +626,55 @@ static struct clk init_clocks_off[] = {
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.0",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.1",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.2",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.3",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.4",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.5",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 11),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.6",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 12),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.7",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 13),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-hdmiphy-i2c",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
@@ -736,7 +736,7 @@ static struct clk init_clocks_off[] = {
 	}
 };
 
-static struct clk init_clocks[] = {
+static struct clk exynos4_init_clocks_on[] = {
 	{
 		.name		= "uart",
 		.devname	= "s5pv210-uart.0",
@@ -770,259 +770,259 @@ static struct clk init_clocks[] = {
 	}
 };
 
-static struct clk clk_pdma0 = {
+static struct clk exynos4_clk_pdma0 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.0",
 	.enable		= exynos4_clk_ip_fsys_ctrl,
 	.ctrlbit	= (1 << 0),
 };
 
-static struct clk clk_pdma1 = {
+static struct clk exynos4_clk_pdma1 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.1",
 	.enable		= exynos4_clk_ip_fsys_ctrl,
 	.ctrlbit	= (1 << 1),
 };
 
-struct clk *clkset_group_list[] = {
+struct clk *exynos4_clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,
-	[2] = &clk_sclk_hdmi27m,
-	[3] = &clk_sclk_usbphy0,
-	[4] = &clk_sclk_usbphy1,
-	[5] = &clk_sclk_hdmiphy,
-	[6] = &clk_mout_mpll.clk,
-	[7] = &clk_mout_epll.clk,
-	[8] = &clk_sclk_vpll.clk,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &exynos4_clk_sclk_usbphy1,
+	[5] = &exynos4_clk_sclk_hdmiphy,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
 };
 
-struct clksrc_sources clkset_group = {
-	.sources	= clkset_group_list,
-	.nr_sources	= ARRAY_SIZE(clkset_group_list),
+struct clksrc_sources exynos4_clkset_group = {
+	.sources	= exynos4_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_group_list),
 };
 
-static struct clk *clkset_mout_g2d0_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d0 = {
-	.sources	= clkset_mout_g2d0_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d0_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+	.sources	= exynos4_clkset_mout_g2d0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 };
 
-static struct clksrc_clk clk_mout_g2d0 = {
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
 	.clk	= {
 		.name		= "mout_g2d0",
 	},
-	.sources = &clkset_mout_g2d0,
-	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_mout_g2d0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_mout_g2d1_list[] = {
-	[0] = &clk_mout_epll.clk,
-	[1] = &clk_sclk_vpll.clk,
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d1 = {
-	.sources	= clkset_mout_g2d1_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d1_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+	.sources	= exynos4_clkset_mout_g2d1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 };
 
-static struct clksrc_clk clk_mout_g2d1 = {
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
 	.clk	= {
 		.name		= "mout_g2d1",
 	},
-	.sources = &clkset_mout_g2d1,
-	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_g2d1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 };
 
-static struct clk *clkset_mout_g2d_list[] = {
-	[0] = &clk_mout_g2d0.clk,
-	[1] = &clk_mout_g2d1.clk,
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+	[0] = &exynos4_clk_mout_g2d0.clk,
+	[1] = &exynos4_clk_mout_g2d1.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d = {
-	.sources	= clkset_mout_g2d_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+	.sources	= exynos4_clkset_mout_g2d_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
 };
 
-static struct clk *clkset_mout_mfc0_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc0 = {
-	.sources	= clkset_mout_mfc0_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc0_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+	.sources	= exynos4_clkset_mout_mfc0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 };
 
-static struct clksrc_clk clk_mout_mfc0 = {
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 	.clk	= {
 		.name		= "mout_mfc0",
 	},
-	.sources = &clkset_mout_mfc0,
-	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_mout_mfc0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_mout_mfc1_list[] = {
-	[0] = &clk_mout_epll.clk,
-	[1] = &clk_sclk_vpll.clk,
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc1 = {
-	.sources	= clkset_mout_mfc1_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc1_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+	.sources	= exynos4_clkset_mout_mfc1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 };
 
-static struct clksrc_clk clk_mout_mfc1 = {
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 	.clk	= {
 		.name		= "mout_mfc1",
 	},
-	.sources = &clkset_mout_mfc1,
-	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_mfc1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 };
 
-static struct clk *clkset_mout_mfc_list[] = {
-	[0] = &clk_mout_mfc0.clk,
-	[1] = &clk_mout_mfc1.clk,
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+	[0] = &exynos4_clk_mout_mfc0.clk,
+	[1] = &exynos4_clk_mout_mfc1.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc = {
-	.sources	= clkset_mout_mfc_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+	.sources	= exynos4_clkset_mout_mfc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 };
 
-static struct clk *clkset_sclk_dac_list[] = {
-	[0] = &clk_sclk_vpll.clk,
-	[1] = &clk_sclk_hdmiphy,
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+	[0] = &exynos4_clk_sclk_vpll.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
 };
 
-static struct clksrc_sources clkset_sclk_dac = {
-	.sources	= clkset_sclk_dac_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_dac_list),
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+	.sources	= exynos4_clkset_sclk_dac_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 };
 
-static struct clksrc_clk clk_sclk_dac = {
+static struct clksrc_clk exynos4_clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 8),
 	},
-	.sources = &clkset_sclk_dac,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+	.sources = &exynos4_clkset_sclk_dac,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_pixel = {
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
 	.clk		= {
 		.name		= "sclk_pixel",
-		.parent		= &clk_sclk_vpll.clk,
+		.parent		= &exynos4_clk_sclk_vpll.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 };
 
-static struct clk *clkset_sclk_hdmi_list[] = {
-	[0] = &clk_sclk_pixel.clk,
-	[1] = &clk_sclk_hdmiphy,
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos4_clk_sclk_pixel.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
 };
 
-static struct clksrc_sources clkset_sclk_hdmi = {
-	.sources	= clkset_sclk_hdmi_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_hdmi_list),
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+	.sources	= exynos4_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 };
 
-static struct clksrc_clk clk_sclk_hdmi = {
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources = &clkset_sclk_hdmi,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_sclk_mixer_list[] = {
-	[0] = &clk_sclk_dac.clk,
-	[1] = &clk_sclk_hdmi.clk,
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+	[0] = &exynos4_clk_sclk_dac.clk,
+	[1] = &exynos4_clk_sclk_hdmi.clk,
 };
 
-static struct clksrc_sources clkset_sclk_mixer = {
-	.sources	= clkset_sclk_mixer_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_mixer_list),
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+	.sources	= exynos4_clkset_sclk_mixer_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 };
 
-static struct clksrc_clk clk_sclk_mixer = {
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
 	.clk	= {
 		.name		= "sclk_mixer",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 4),
 	},
-	.sources = &clkset_sclk_mixer,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_sclk_mixer,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk *sclk_tv[] = {
-	&clk_sclk_dac,
-	&clk_sclk_pixel,
-	&clk_sclk_hdmi,
-	&clk_sclk_mixer,
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+	&exynos4_clk_sclk_dac,
+	&exynos4_clk_sclk_pixel,
+	&exynos4_clk_sclk_hdmi,
+	&exynos4_clk_sclk_mixer,
 };
 
-static struct clksrc_clk clk_dout_mmc0 = {
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 	.clk	= {
 		.name		= "dout_mmc0",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+	.sourc