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authorLinus Torvalds <torvalds@linux-foundation.org>2009-01-07 11:56:29 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2009-01-07 11:56:29 -0800
commit52fefcec97c25b15887e6a9a885ca54e7f7c0928 (patch)
tree4898112a7fb30c20a9da3aefe9fdc7fdebda57a6 /arch/xtensa/include
parenta0e280e0f33f6c859a235fb69a875ed8f3420388 (diff)
parent5fee325e7d2bcbebf1cb38b4ff3a7aa3744c43e3 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6: xtensa: Update platform files to reflect new location of the header files. xtensa: switch to packed struct unaligned access implementation xtensa: Add xt2000 support files. xtensa: move headers files to arch/xtensa/include xtensa: use the new byteorder headers
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r--arch/xtensa/include/asm/Kbuild1
-rw-r--r--arch/xtensa/include/asm/asmmacro.h153
-rw-r--r--arch/xtensa/include/asm/atomic.h299
-rw-r--r--arch/xtensa/include/asm/auxvec.h4
-rw-r--r--arch/xtensa/include/asm/bitops.h132
-rw-r--r--arch/xtensa/include/asm/bootparam.h61
-rw-r--r--arch/xtensa/include/asm/bug.h18
-rw-r--r--arch/xtensa/include/asm/bugs.h18
-rw-r--r--arch/xtensa/include/asm/byteorder.h80
-rw-r--r--arch/xtensa/include/asm/cache.h33
-rw-r--r--arch/xtensa/include/asm/cacheasm.h177
-rw-r--r--arch/xtensa/include/asm/cacheflush.h155
-rw-r--r--arch/xtensa/include/asm/checksum.h250
-rw-r--r--arch/xtensa/include/asm/coprocessor.h177
-rw-r--r--arch/xtensa/include/asm/cpumask.h16
-rw-r--r--arch/xtensa/include/asm/cputime.h6
-rw-r--r--arch/xtensa/include/asm/current.h38
-rw-r--r--arch/xtensa/include/asm/delay.h49
-rw-r--r--arch/xtensa/include/asm/device.h7
-rw-r--r--arch/xtensa/include/asm/div64.h16
-rw-r--r--arch/xtensa/include/asm/dma-mapping.h179
-rw-r--r--arch/xtensa/include/asm/dma.h61
-rw-r--r--arch/xtensa/include/asm/elf.h205
-rw-r--r--arch/xtensa/include/asm/emergency-restart.h6
-rw-r--r--arch/xtensa/include/asm/errno.h16
-rw-r--r--arch/xtensa/include/asm/fb.h12
-rw-r--r--arch/xtensa/include/asm/fcntl.h1
-rw-r--r--arch/xtensa/include/asm/futex.h1
-rw-r--r--arch/xtensa/include/asm/hardirq.h28
-rw-r--r--arch/xtensa/include/asm/highmem.h17
-rw-r--r--arch/xtensa/include/asm/hw_irq.h14
-rw-r--r--arch/xtensa/include/asm/io.h200
-rw-r--r--arch/xtensa/include/asm/ioctl.h1
-rw-r--r--arch/xtensa/include/asm/ioctls.h116
-rw-r--r--arch/xtensa/include/asm/ipcbuf.h37
-rw-r--r--arch/xtensa/include/asm/irq.h30
-rw-r--r--arch/xtensa/include/asm/irq_regs.h1
-rw-r--r--arch/xtensa/include/asm/kdebug.h1
-rw-r--r--arch/xtensa/include/asm/kmap_types.h31
-rw-r--r--arch/xtensa/include/asm/linkage.h16
-rw-r--r--arch/xtensa/include/asm/local.h16
-rw-r--r--arch/xtensa/include/asm/mman.h84
-rw-r--r--arch/xtensa/include/asm/mmu.h17
-rw-r--r--arch/xtensa/include/asm/mmu_context.h136
-rw-r--r--arch/xtensa/include/asm/module.h27
-rw-r--r--arch/xtensa/include/asm/msgbuf.h48
-rw-r--r--arch/xtensa/include/asm/mutex.h9
-rw-r--r--arch/xtensa/include/asm/page.h174
-rw-r--r--arch/xtensa/include/asm/param.h34
-rw-r--r--arch/xtensa/include/asm/pci-bridge.h88
-rw-r--r--arch/xtensa/include/asm/pci.h82
-rw-r--r--arch/xtensa/include/asm/percpu.h16
-rw-r--r--arch/xtensa/include/asm/pgalloc.h73
-rw-r--r--arch/xtensa/include/asm/pgtable.h416
-rw-r--r--arch/xtensa/include/asm/platform.h89
-rw-r--r--arch/xtensa/include/asm/poll.h20
-rw-r--r--arch/xtensa/include/asm/posix_types.h122
-rw-r--r--arch/xtensa/include/asm/processor.h193
-rw-r--r--arch/xtensa/include/asm/ptrace.h135
-rw-r--r--arch/xtensa/include/asm/regs.h145
-rw-r--r--arch/xtensa/include/asm/resource.h16
-rw-r--r--arch/xtensa/include/asm/rmap.h16
-rw-r--r--arch/xtensa/include/asm/rwsem.h168
-rw-r--r--arch/xtensa/include/asm/scatterlist.h39
-rw-r--r--arch/xtensa/include/asm/sections.h16
-rw-r--r--arch/xtensa/include/asm/segment.h16
-rw-r--r--arch/xtensa/include/asm/sembuf.h44
-rw-r--r--arch/xtensa/include/asm/serial.h18
-rw-r--r--arch/xtensa/include/asm/setup.h16
-rw-r--r--arch/xtensa/include/asm/shmbuf.h71
-rw-r--r--arch/xtensa/include/asm/shmparam.h21
-rw-r--r--arch/xtensa/include/asm/sigcontext.h28
-rw-r--r--arch/xtensa/include/asm/siginfo.h16
-rw-r--r--arch/xtensa/include/asm/signal.h172
-rw-r--r--arch/xtensa/include/asm/smp.h27
-rw-r--r--arch/xtensa/include/asm/socket.h68
-rw-r--r--arch/xtensa/include/asm/sockios.h31
-rw-r--r--arch/xtensa/include/asm/spinlock.h16
-rw-r--r--arch/xtensa/include/asm/stat.h59
-rw-r--r--arch/xtensa/include/asm/statfs.h17
-rw-r--r--arch/xtensa/include/asm/string.h124
-rw-r--r--arch/xtensa/include/asm/syscall.h42
-rw-r--r--arch/xtensa/include/asm/system.h215
-rw-r--r--arch/xtensa/include/asm/termbits.h219
-rw-r--r--arch/xtensa/include/asm/termios.h105
-rw-r--r--arch/xtensa/include/asm/thread_info.h164
-rw-r--r--arch/xtensa/include/asm/timex.h96
-rw-r--r--arch/xtensa/include/asm/tlb.h47
-rw-r--r--arch/xtensa/include/asm/tlbflush.h191
-rw-r--r--arch/xtensa/include/asm/topology.h16
-rw-r--r--arch/xtensa/include/asm/types.h42
-rw-r--r--arch/xtensa/include/asm/uaccess.h500
-rw-r--r--arch/xtensa/include/asm/ucontext.h22
-rw-r--r--arch/xtensa/include/asm/unaligned.h29
-rw-r--r--arch/xtensa/include/asm/unistd.h735
-rw-r--r--arch/xtensa/include/asm/user.h20
-rw-r--r--arch/xtensa/include/asm/vga.h19
-rw-r--r--arch/xtensa/include/asm/xor.h16
98 files changed, 8064 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild
new file mode 100644
index 00000000000..c68e1680da0
--- /dev/null
+++ b/arch/xtensa/include/asm/Kbuild
@@ -0,0 +1 @@
+include include/asm-generic/Kbuild.asm
diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
new file mode 100644
index 00000000000..755320f6e0b
--- /dev/null
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -0,0 +1,153 @@
+/*
+ * include/asm-xtensa/asmmacro.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ASMMACRO_H
+#define _XTENSA_ASMMACRO_H
+
+#include <variant/core.h>
+
+/*
+ * Some little helpers for loops. Use zero-overhead-loops
+ * where applicable and if supported by the processor.
+ *
+ * __loopi ar, at, size, inc
+ * ar register initialized with the start address
+ * at scratch register used by macro
+ * size size immediate value
+ * inc increment
+ *
+ * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
+ * ar register initialized with the start address
+ * as register initialized with the size
+ * at scratch register use by macro
+ * inc_log2 increment [in log2]
+ * mask_log2 mask [in log2]
+ * cond true condition (used in loop'cond')
+ * ncond false condition (used in b'ncond')
+ *
+ * __loop as
+ * restart loop. 'as' register must not have been modified!
+ *
+ * __endla ar, at, incr
+ * ar start address (modified)
+ * as scratch register used by macro
+ * inc increment
+ */
+
+/*
+ * loop for given size as immediate
+ */
+
+ .macro __loopi ar, at, size, incr
+
+#if XCHAL_HAVE_LOOPS
+ movi \at, ((\size + \incr - 1) / (\incr))
+ loop \at, 99f
+#else
+ addi \at, \ar, \size
+ 98:
+#endif
+
+ .endm
+
+/*
+ * loop for given size in register
+ */
+
+ .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
+
+#if XCHAL_HAVE_LOOPS
+ .ifgt \incr_log2 - 1
+ addi \at, \as, (1 << \incr_log2) - 1
+ .ifnc \mask_log2,
+ extui \at, \at, \incr_log2, \mask_log2
+ .else
+ srli \at, \at, \incr_log2
+ .endif
+ .endif
+ loop\cond \at, 99f
+#else
+ .ifnc \mask_log2,
+ extui \at, \as, \incr_log2, \mask_log2
+ .else
+ .ifnc \ncond,
+ srli \at, \as, \incr_log2
+ .endif
+ .endif
+ .ifnc \ncond,
+ b\ncond \at, 99f
+
+ .endif
+ .ifnc \mask_log2,
+ slli \at, \at, \incr_log2
+ add \at, \ar, \at
+ .else
+ add \at, \ar, \as
+ .endif
+#endif
+ 98:
+
+ .endm
+
+/*
+ * loop from ar to ax
+ */
+
+ .macro __loopt ar, as, at, incr_log2
+
+#if XCHAL_HAVE_LOOPS
+ sub \at, \as, \ar
+ .ifgt \incr_log2 - 1
+ addi \at, \at, (1 << \incr_log2) - 1
+ srli \at, \at, \incr_log2
+ .endif
+ loop \at, 99f
+#else
+ 98:
+#endif
+
+ .endm
+
+/*
+ * restart loop. registers must be unchanged
+ */
+
+ .macro __loop as
+
+#if XCHAL_HAVE_LOOPS
+ loop \as, 99f
+#else
+ 98:
+#endif
+
+ .endm
+
+/*
+ * end of loop with no increment of the address.
+ */
+
+ .macro __endl ar, as
+#if !XCHAL_HAVE_LOOPS
+ bltu \ar, \as, 98b
+#endif
+ 99:
+ .endm
+
+/*
+ * end of loop with increment of the address.
+ */
+
+ .macro __endla ar, as, incr
+ addi \ar, \ar, \incr
+ __endl \ar \as
+ .endm
+
+
+#endif /* _XTENSA_ASMMACRO_H */
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
new file mode 100644
index 00000000000..67ad67bed8c
--- /dev/null
+++ b/arch/xtensa/include/asm/atomic.h
@@ -0,0 +1,299 @@
+/*
+ * include/asm-xtensa/atomic.h
+ *
+ * Atomic operations that C can't guarantee us. Useful for resource counting..
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ATOMIC_H
+#define _XTENSA_ATOMIC_H
+
+#include <linux/stringify.h>
+#include <linux/types.h>
+
+#ifdef __KERNEL__
+#include <asm/processor.h>
+#include <asm/system.h>
+
+#define ATOMIC_INIT(i) { (i) }
+
+/*
+ * This Xtensa implementation assumes that the right mechanism
+ * for exclusion is for locking interrupts to level 1.
+ *
+ * Locking interrupts looks like this:
+ *
+ * rsil a15, 1
+ * <code>
+ * wsr a15, PS
+ * rsync
+ *
+ * Note that a15 is used here because the register allocation
+ * done by the compiler is not guaranteed and a window overflow
+ * may not occur between the rsil and wsr instructions. By using
+ * a15 in the rsil, the machine is guaranteed to be in a state
+ * where no register reference will cause an overflow.
+ */
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+#define atomic_read(v) ((v)->counter)
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+#define atomic_set(v,i) ((v)->counter = (i))
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, atomic_t * v)
+{
+ unsigned int vval;
+
+ __asm__ __volatile__(
+ "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
+ "l32i %0, %2, 0 \n\t"
+ "add %0, %0, %1 \n\t"
+ "s32i %0, %2, 0 \n\t"
+ "wsr a15, "__stringify(PS)" \n\t"
+ "rsync \n"
+ : "=&a" (vval)
+ : "a" (i), "a" (v)
+ : "a15", "memory"
+ );
+}
+
+/**
+ * atomic_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ unsigned int vval;
+
+ __asm__ __volatile__(
+ "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
+ "l32i %0, %2, 0 \n\t"
+ "sub %0, %0, %1 \n\t"
+ "s32i %0, %2, 0 \n\t"
+ "wsr a15, "__stringify(PS)" \n\t"
+ "rsync \n"
+ : "=&a" (vval)
+ : "a" (i), "a" (v)
+ : "a15", "memory"
+ );
+}
+
+/*
+ * We use atomic_{add|sub}_return to define other functions.
+ */
+
+static inline int atomic_add_return(int i, atomic_t * v)
+{
+ unsigned int vval;
+
+ __asm__ __volatile__(
+ "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
+ "l32i %0, %2, 0 \n\t"
+ "add %0, %0, %1 \n\t"
+ "s32i %0, %2, 0 \n\t"
+ "wsr a15, "__stringify(PS)" \n\t"
+ "rsync \n"
+ : "=&a" (vval)
+ : "a" (i), "a" (v)
+ : "a15", "memory"
+ );
+
+ return vval;
+}
+
+static inline int atomic_sub_return(int i, atomic_t * v)
+{
+ unsigned int vval;
+
+ __asm__ __volatile__(
+ "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
+ "l32i %0, %2, 0 \n\t"
+ "sub %0, %0, %1 \n\t"
+ "s32i %0, %2, 0 \n\t"
+ "wsr a15, "__stringify(PS)" \n\t"
+ "rsync \n"
+ : "=&a" (vval)
+ : "a" (i), "a" (v)
+ : "a15", "memory"
+ );
+
+ return vval;
+}
+
+/**
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc(v) atomic_add(1,(v))
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc_return(v) atomic_