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authorCyrill Gorcunov <gorcunov@openvz.org>2011-03-28 00:46:11 +0400
committerIngo Molnar <mingo@elte.hu>2011-03-29 09:36:33 +0200
commit1d321881afb955bba1e0a8f50d3a04e111fcb581 (patch)
tree6645bb9134afcea5ff5a6543c0427400c7306c4d /arch/x86/kernel/cpu/perf_event_p4.c
parent89078d572eb9ce8d4c04264b8b0ba86de0d74c8f (diff)
perf, x86: P4 PMU - clean up the code a bit
No change on the functional level, just align the table properly. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <4D8FA213.5050108@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_p4.c')
-rw-r--r--arch/x86/kernel/cpu/perf_event_p4.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index c2520e178d3..8ff882fdb1c 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -468,7 +468,7 @@ static struct p4_event_bind p4_event_bind_map[] = {
.opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
.escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
.escr_emask =
- P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
+ P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
.cntr = { {12, 13, 16}, {14, 15, 17} },
},
[P4_EVENT_X87_ASSIST] = {