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authorBoris Ostrovsky <boris.ostrovsky@amd.com>2013-01-29 16:32:49 -0500
committerH. Peter Anvin <hpa@linux.intel.com>2013-01-31 13:35:38 -0800
commitf0322bd341fd63261527bf84afd3272bcc2e8dd3 (patch)
tree40138ddb8827ab5945c8d13b5ae731bc92018443 /arch/x86/kernel/cpu/amd.c
parent6bf08a8dcd1ef13e542f08fc3b1ce6cf64ae63b6 (diff)
x86, AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10 processors, instead converting what would be WC+ memory to CD type. On guests using nested pages this could result in performance degradation. This patch enables WC+. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-ostr@amd64.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu/amd.c')
-rw-r--r--arch/x86/kernel/cpu/amd.c21
1 files changed, 16 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b685a0..721ef3208eb 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c->x86 > 0x11)
set_cpu_cap(c, X86_FEATURE_ARAT);
- /*
- * Disable GART TLB Walk Errors on Fam10h. We do this here
- * because this is always needed when GART is enabled, even in a
- * kernel which has no MCE support built in.
- */
if (c->x86 == 0x10) {
/*
+ * Disable GART TLB Walk Errors on Fam10h. We do this here
+ * because this is always needed when GART is enabled, even in a
+ * kernel which has no MCE support built in.
* BIOS should disable GartTlbWlk Errors themself. If
* it doesn't do it here as suggested by the BKDG.
*
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
mask |= (1 << 10);
wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
}
+
+ /*
+ * On family 10h BIOS may not have properly enabled WC+ support,
+ * causing it to be converted to CD memtype. This may result in
+ * performance degradation for certain nested-paging guests.
+ * Prevent this conversion by clearing bit 24 in
+ * MSR_AMD64_BU_CFG2.
+ */
+ if (c->x86 == 0x10) {
+ rdmsrl(MSR_AMD64_BU_CFG2, value);
+ value &= ~(1ULL << 24);
+ wrmsrl(MSR_AMD64_BU_CFG2, value);
+ }
}
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);