diff options
| author | Robert Richter <robert.richter@amd.com> | 2010-09-24 15:54:43 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2010-12-19 11:43:08 +0100 |
| commit | da169f5df2764a6a937cb3b07562e269edfb1c0e (patch) | |
| tree | aa3998eafd72b7ab79c8e13ec07bc2546110ebab /arch/x86/include | |
| parent | 30570bced107243d5227527dd5317b22883dcf0c (diff) | |
oprofile, x86: Add support for 6 counters (AMD family 15h)
This patch adds support for up to 6 hardware counters for AMD family
15h cpus. There is a new MSR range for hardware counters beginning at
MSRC001_0200 Performance Event Select (PERF_CTL0).
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6b89f5e8602..86030f63ba0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -123,6 +123,10 @@ #define MSR_AMD64_IBSCTL 0xc001103a #define MSR_AMD64_IBSBRTARGET 0xc001103b +/* Fam 15h MSRs */ +#define MSR_F15H_PERF_CTL 0xc0010200 +#define MSR_F15H_PERF_CTR 0xc0010201 + /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 #define FAM10H_MMIO_CONF_ENABLE (1<<0) |