diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-06-25 17:03:27 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-07-06 13:41:46 -0400 |
| commit | c78095bd8c77fca2619769ff8efb639fd100e373 (patch) | |
| tree | 9841462486a97a3733f0e5b789e8f6dce47ca62f /arch/tile/include/asm | |
| parent | 2db098278118ed58f4b407ceda691e349df043ce (diff) | |
arch/tile: Split the icache flush code off to a generic <arch> header.
This code is used in other places in our system than in Linux, so
to share it we now implement it as an inline function in our low-level
<arch> headers, and instantiate it in one file in Linux's arch/tile/lib.
The file is now cacheflush.c and is C code rather than the strangely-named
and assembler-implemented __invalidate_icache.S.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/tile/include/asm')
| -rw-r--r-- | arch/tile/include/asm/cacheflush.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h index 7e2096a4ef7..c5741da4eea 100644 --- a/arch/tile/include/asm/cacheflush.h +++ b/arch/tile/include/asm/cacheflush.h @@ -21,6 +21,7 @@ #include <linux/mm.h> #include <linux/cache.h> #include <asm/system.h> +#include <arch/icache.h> /* Caches are physically-indexed and so don't need special treatment */ #define flush_cache_all() do { } while (0) @@ -37,14 +38,8 @@ #define flush_icache_page(vma, pg) do { } while (0) #define flush_icache_user_range(vma, pg, adr, len) do { } while (0) -/* See "arch/tile/lib/__invalidate_icache.S". */ -extern void __invalidate_icache(unsigned long start, unsigned long size); - /* Flush the icache just on this cpu */ -static inline void __flush_icache_range(unsigned long start, unsigned long end) -{ - __invalidate_icache(start, end - start); -} +extern void __flush_icache_range(unsigned long start, unsigned long end); /* Flush the entire icache on this cpu. */ #define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE()) |