diff options
| author | David S. Miller <davem@sunset.davemloft.net> | 2006-02-11 00:29:34 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 01:12:16 -0800 |
| commit | 36a68e77c554f1ef1c206fd618e6daf82d3e38a3 (patch) | |
| tree | 59a4591b76ef18e54b5b1b2687268e0dd6bb69ef /arch/sparc64/kernel/tsb.S | |
| parent | 12eaa328f9fb2d3fcb5afb682c762690d05a3cd8 (diff) | |
[SPARC64]: Simplify sun4v TLB handling using macros.
There was also a bug in sun4v_itlb_miss, it loaded the
MMU Fault Status base into %g3 instead of %g2.
This pointed out a fast path for TSB miss processing,
since we have %g2 with the MMU Fault Status base, we
can use that to quickly load up the PGD phys address.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/tsb.S')
| -rw-r--r-- | arch/sparc64/kernel/tsb.S | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S index 8a9351258af..667dcb077be 100644 --- a/arch/sparc64/kernel/tsb.S +++ b/arch/sparc64/kernel/tsb.S @@ -25,26 +25,24 @@ */ tsb_miss_dtlb: mov TLB_TAG_ACCESS, %g4 - ldxa [%g4] ASI_DMMU, %g4 ba,pt %xcc, tsb_miss_page_table_walk - nop + ldxa [%g4] ASI_DMMU, %g4 tsb_miss_itlb: mov TLB_TAG_ACCESS, %g4 - ldxa [%g4] ASI_IMMU, %g4 ba,pt %xcc, tsb_miss_page_table_walk - nop + ldxa [%g4] ASI_IMMU, %g4 - /* The sun4v TLB miss handlers jump directly here instead - * of tsb_miss_{d,i}tlb with registers setup as follows: - * - * %g4: missing virtual address - * %g1: TSB entry address loaded - * %g6: TAG TARGET ((vaddr >> 22) | (ctx << 48)) + /* At this point we have: + * %g4 -- missing virtual address + * %g1 -- TSB entry address + * %g6 -- TAG TARGET ((vaddr >> 22) | (ctx << 48)) */ tsb_miss_page_table_walk: TRAP_LOAD_PGD_PHYS(%g7, %g5) + /* And now we have the PGD base physical address in %g7. */ +tsb_miss_page_table_walk_sun4v_fastpath: USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault) tsb_reload: |