Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

1 files changed, 1956 insertions, 0 deletions

diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
new file mode 100644
index 00000000000..b448166f5da
--- /dev/null
+++ b/arch/sparc/kernel/entry.S
@@ -0,0 +1,1956 @@
+/* $Id: entry.S,v 1.170 2001/11/13 00:57:05 davem Exp $
+ * arch/sparc/kernel/entry.S:  Sparc trap low-level entry points.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 Eddie C. Dost   (ecd@skynet.be)
+ * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
+ * Copyright (C) 1996-1999 Jakub Jelinek   (jj@sunsite.mff.cuni.cz)
+ * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
+ */
+
+#include <linux/config.h>
+#include <linux/errno.h>
+
+#include <asm/head.h>
+#include <asm/asi.h>
+#include <asm/smp.h>
+#include <asm/kgdb.h>
+#include <asm/contregs.h>
+#include <asm/ptrace.h>
+#include <asm/asm_offsets.h>
+#include <asm/psr.h>
+#include <asm/vaddrs.h>
+#include <asm/memreg.h>
+#include <asm/page.h>
+#ifdef CONFIG_SUN4
+#include <asm/pgtsun4.h>
+#else
+#include <asm/pgtsun4c.h>
+#endif
+#include <asm/winmacro.h>
+#include <asm/signal.h>
+#include <asm/obio.h>
+#include <asm/mxcc.h>
+#include <asm/thread_info.h>
+#include <asm/param.h>
+
+#include <asm/asmmacro.h>
+
+#define curptr      g6
+
+#define NR_SYSCALLS 284      /* Each OS is different... */
+
+/* These are just handy. */
+#define _SV	save	%sp, -STACKFRAME_SZ, %sp
+#define _RS     restore 
+
+#define FLUSH_ALL_KERNEL_WINDOWS \
+	_SV; _SV; _SV; _SV; _SV; _SV; _SV; \
+	_RS; _RS; _RS; _RS; _RS; _RS; _RS;
+
+/* First, KGDB low level things.  This is a rewrite
+ * of the routines found in the sparc-stub.c asm() statement
+ * from the gdb distribution.  This is also dual-purpose
+ * as a software trap for userlevel programs.
+ */
+	.data
+	.align	4
+
+in_trap_handler:
+	.word	0
+
+	.text
+	.align	4
+
+#if 0 /* kgdb is dropped from 2.5.33 */
+! This function is called when any SPARC trap (except window overflow or
+! underflow) occurs.  It makes sure that the invalid register window is still
+! available before jumping into C code.  It will also restore the world if you
+! return from handle_exception.
+
+	.globl	trap_low
+trap_low:
+	rd	%wim, %l3
+	SAVE_ALL
+
+	sethi	%hi(in_trap_handler), %l4
+	ld	[%lo(in_trap_handler) + %l4], %l5
+	inc	%l5
+	st	%l5, [%lo(in_trap_handler) + %l4]
+
+	/* Make sure kgdb sees the same state we just saved. */
+	LOAD_PT_GLOBALS(sp)
+	LOAD_PT_INS(sp)
+	ld	[%sp + STACKFRAME_SZ + PT_Y], %l4
+	ld	[%sp + STACKFRAME_SZ + PT_WIM], %l3
+	ld	[%sp + STACKFRAME_SZ + PT_PSR], %l0
+	ld	[%sp + STACKFRAME_SZ + PT_PC], %l1
+	ld	[%sp + STACKFRAME_SZ + PT_NPC], %l2
+	rd	%tbr, %l5	/* Never changes... */
+
+	/* Make kgdb exception frame. */	
+	sub	%sp,(16+1+6+1+72)*4,%sp	! Make room for input & locals
+ 					! + hidden arg + arg spill
+					! + doubleword alignment
+					! + registers[72] local var
+	SAVE_KGDB_GLOBALS(sp)
+	SAVE_KGDB_INS(sp)
+	SAVE_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2)
+
+	/* We are increasing PIL, so two writes. */
+	or	%l0, PSR_PIL, %l0
+	wr	%l0, 0, %psr
+	WRITE_PAUSE
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	call	handle_exception
+	 add	%sp, STACKFRAME_SZ, %o0	! Pass address of registers
+
+	/* Load new kgdb register set. */
+	LOAD_KGDB_GLOBALS(sp)
+	LOAD_KGDB_INS(sp)
+	LOAD_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2)
+	wr      %l4, 0x0, %y
+
+	sethi	%hi(in_trap_handler), %l4
+	ld	[%lo(in_trap_handler) + %l4], %l5
+	dec	%l5
+	st	%l5, [%lo(in_trap_handler) + %l4]
+
+	add	%sp,(16+1+6+1+72)*4,%sp	! Undo the kgdb trap frame.
+
+	/* Now take what kgdb did and place it into the pt_regs
+	 * frame which SparcLinux RESTORE_ALL understands.,
+	 */
+	STORE_PT_INS(sp)
+	STORE_PT_GLOBALS(sp)
+	STORE_PT_YREG(sp, g2)
+	STORE_PT_PRIV(sp, l0, l1, l2)
+
+	RESTORE_ALL
+#endif
+
+#ifdef CONFIG_BLK_DEV_FD
+	.text
+	.align	4
+	.globl	floppy_hardint
+floppy_hardint:
+	/*
+	 * This code cannot touch registers %l0 %l1 and %l2
+	 * because SAVE_ALL depends on their values. It depends
+	 * on %l3 also, but we regenerate it before a call.
+	 * Other registers are:
+	 * %l3 -- base address of fdc registers
+	 * %l4 -- pdma_vaddr
+	 * %l5 -- scratch for ld/st address
+	 * %l6 -- pdma_size
+	 * %l7 -- scratch [floppy byte, ld/st address, aux. data]
+	 */
+
+	/* Do we have work to do? */
+	sethi	%hi(doing_pdma), %l7
+	ld	[%l7 + %lo(doing_pdma)], %l7
+	cmp	%l7, 0
+	be	floppy_dosoftint
+	 nop
+
+	/* Load fdc register base */
+	sethi	%hi(fdc_status), %l3
+	ld	[%l3 + %lo(fdc_status)], %l3
+
+	/* Setup register addresses */
+	sethi	%hi(pdma_vaddr), %l5	! transfer buffer
+	ld	[%l5 + %lo(pdma_vaddr)], %l4
+	sethi	%hi(pdma_size), %l5	! bytes to go
+	ld	[%l5 + %lo(pdma_size)], %l6
+next_byte:
+  	ldub	[%l3], %l7
+
+	andcc	%l7, 0x80, %g0		! Does fifo still have data
+	bz	floppy_fifo_emptied	! fifo has been emptied...
+	 andcc	%l7, 0x20, %g0		! in non-dma mode still?
+	bz	floppy_overrun		! nope, overrun
+	 andcc	%l7, 0x40, %g0		! 0=write 1=read
+	bz	floppy_write
+	 sub	%l6, 0x1, %l6
+
+	/* Ok, actually read this byte */
+	ldub	[%l3 + 1], %l7
+	orcc	%g0, %l6, %g0
+	stb	%l7, [%l4]
+	bne	next_byte
+	 add	%l4, 0x1, %l4
+
+	b	floppy_tdone
+	 nop
+
+floppy_write:
+	/* Ok, actually write this byte */
+	ldub	[%l4], %l7
+	orcc	%g0, %l6, %g0
+	stb	%l7, [%l3 + 1]
+	bne	next_byte
+	 add	%l4, 0x1, %l4
+
+	/* fall through... */
+floppy_tdone:
+	sethi	%hi(pdma_vaddr), %l5
+	st	%l4, [%l5 + %lo(pdma_vaddr)]
+	sethi	%hi(pdma_size), %l5
+	st	%l6, [%l5 + %lo(pdma_size)]
+	/* Flip terminal count pin */
+	set	auxio_register, %l7
+	ld	[%l7], %l7
+
+	set	sparc_cpu_model, %l5
+	ld	[%l5], %l5
+	subcc   %l5, 1, %g0		/* enum { sun4c = 1 }; */
+	be	1f
+	 ldub	[%l7], %l5
+
+	or	%l5, 0xc2, %l5
+	stb	%l5, [%l7]
+	andn    %l5, 0x02, %l5
+	b	2f
+	 nop
+
+1:
+	or      %l5, 0xf4, %l5
+	stb     %l5, [%l7]
+	andn    %l5, 0x04, %l5
+
+2:
+	/* Kill some time so the bits set */
+	WRITE_PAUSE
+	WRITE_PAUSE
+
+	stb     %l5, [%l7]
+
+	/* Prevent recursion */
+	sethi	%hi(doing_pdma), %l7
+	b	floppy_dosoftint
+	 st	%g0, [%l7 + %lo(doing_pdma)]
+
+	/* We emptied the FIFO, but we haven't read everything
+	 * as of yet.  Store the current transfer address and
+	 * bytes left to read so we can continue when the next
+	 * fast IRQ comes in.
+	 */
+floppy_fifo_emptied:
+	sethi	%hi(pdma_vaddr), %l5
+	st	%l4, [%l5 + %lo(pdma_vaddr)]
+	sethi	%hi(pdma_size), %l7
+	st	%l6, [%l7 + %lo(pdma_size)]
+
+	/* Restore condition codes */
+	wr	%l0, 0x0, %psr
+	WRITE_PAUSE
+
+	jmp	%l1
+	rett	%l2
+
+floppy_overrun:
+	sethi	%hi(pdma_vaddr), %l5
+	st	%l4, [%l5 + %lo(pdma_vaddr)]
+	sethi	%hi(pdma_size), %l5
+	st	%l6, [%l5 + %lo(pdma_size)]
+	/* Prevent recursion */
+	sethi	%hi(doing_pdma), %l7
+	st	%g0, [%l7 + %lo(doing_pdma)]
+
+	/* fall through... */
+floppy_dosoftint:
+	rd	%wim, %l3
+	SAVE_ALL
+
+	/* Set all IRQs off. */
+	or	%l0, PSR_PIL, %l4
+	wr	%l4, 0x0, %psr
+	WRITE_PAUSE
+	wr	%l4, PSR_ET, %psr
+	WRITE_PAUSE
+
+	mov	11, %o0			! floppy irq level (unused anyway)
+	mov	%g0, %o1		! devid is not used in fast interrupts
+	call	sparc_floppy_irq
+	 add	%sp, STACKFRAME_SZ, %o2	! struct pt_regs *regs
+
+	RESTORE_ALL
+	
+#endif /* (CONFIG_BLK_DEV_FD) */
+
+	/* Bad trap handler */
+	.globl	bad_trap_handler
+bad_trap_handler:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0	! pt_regs
+	call	do_hw_interrupt
+	 mov	%l7, %o1		! trap number
+
+	RESTORE_ALL
+	
+/* For now all IRQ's not registered get sent here. handler_irq() will
+ * see if a routine is registered to handle this interrupt and if not
+ * it will say so on the console.
+ */
+
+	.align	4
+	.globl	real_irq_entry, patch_handler_irq
+real_irq_entry:
+	SAVE_ALL
+
+#ifdef CONFIG_SMP
+	.globl	patchme_maybe_smp_msg
+
+	cmp	%l7, 12
+patchme_maybe_smp_msg:
+	bgu	maybe_smp4m_msg
+	 nop
+#endif
+
+real_irq_continue:
+	or	%l0, PSR_PIL, %g2
+	wr	%g2, 0x0, %psr
+	WRITE_PAUSE
+	wr	%g2, PSR_ET, %psr
+	WRITE_PAUSE
+	mov	%l7, %o0		! irq level
+patch_handler_irq:
+	call	handler_irq
+	 add	%sp, STACKFRAME_SZ, %o1	! pt_regs ptr
+	or	%l0, PSR_PIL, %g2	! restore PIL after handler_irq
+	wr	%g2, PSR_ET, %psr	! keep ET up
+	WRITE_PAUSE
+
+	RESTORE_ALL
+
+#ifdef CONFIG_SMP
+	/* SMP per-cpu ticker interrupts are handled specially. */
+smp4m_ticker:
+	bne	real_irq_continue+4
+	 or	%l0, PSR_PIL, %g2
+	wr	%g2, 0x0, %psr
+	WRITE_PAUSE
+	wr	%g2, PSR_ET, %psr
+	WRITE_PAUSE
+	call	smp4m_percpu_timer_interrupt
+	 add	%sp, STACKFRAME_SZ, %o0
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+	RESTORE_ALL
+
+	/* Here is where we check for possible SMP IPI passed to us
+	 * on some level other than 15 which is the NMI and only used
+	 * for cross calls.  That has a separate entry point below.
+	 */
+maybe_smp4m_msg:
+	GET_PROCESSOR4M_ID(o3)
+	set	sun4m_interrupts, %l5
+	ld	[%l5], %o5
+	sethi	%hi(0x40000000), %o2
+	sll	%o3, 12, %o3
+	ld	[%o5 + %o3], %o1
+	andcc	%o1, %o2, %g0
+	be,a	smp4m_ticker
+	 cmp	%l7, 14
+	st	%o2, [%o5 + 0x4]
+	WRITE_PAUSE
+	ld	[%o5], %g0
+	WRITE_PAUSE
+	or	%l0, PSR_PIL, %l4
+	wr	%l4, 0x0, %psr
+	WRITE_PAUSE
+	wr	%l4, PSR_ET, %psr
+	WRITE_PAUSE
+	call	smp_reschedule_irq
+	 nop
+
+	RESTORE_ALL
+
+	.align	4
+	.globl	linux_trap_ipi15_sun4m
+linux_trap_ipi15_sun4m:
+	SAVE_ALL
+	sethi	%hi(0x80000000), %o2
+	GET_PROCESSOR4M_ID(o0)
+	set	sun4m_interrupts, %l5
+	ld	[%l5], %o5
+	sll	%o0, 12, %o0
+	add	%o5, %o0, %o5
+	ld	[%o5], %o3
+	andcc	%o3, %o2, %g0
+	be	1f			! Must be an NMI async memory error
+	 st	%o2, [%o5 + 4]
+	WRITE_PAUSE
+	ld	[%o5], %g0
+	WRITE_PAUSE
+	or	%l0, PSR_PIL, %l4
+	wr	%l4, 0x0, %psr
+	WRITE_PAUSE
+	wr	%l4, PSR_ET, %psr
+	WRITE_PAUSE
+	call	smp4m_cross_call_irq
+	 nop
+	b	ret_trap_lockless_ipi
+	 clr	%l6
+1:
+	/* NMI async memory error handling. */
+	sethi	%hi(0x80000000), %l4
+	sethi	%hi(0x4000), %o3
+	sub	%o5, %o0, %o5
+	add	%o5, %o3, %l5
+	st	%l4, [%l5 + 0xc]
+	WRITE_PAUSE
+	ld	[%l5], %g0
+	WRITE_PAUSE
+	or	%l0, PSR_PIL, %l4
+	wr	%l4, 0x0, %psr
+	WRITE_PAUSE
+	wr	%l4, PSR_ET, %psr
+	WRITE_PAUSE
+	call	sun4m_nmi
+	 nop
+	st	%l4, [%l5 + 0x8]
+	WRITE_PAUSE
+	ld	[%l5], %g0
+	WRITE_PAUSE
+	RESTORE_ALL
+
+	.globl	smp4d_ticker
+	/* SMP per-cpu ticker interrupts are handled specially. */
+smp4d_ticker:
+	SAVE_ALL
+	or	%l0, PSR_PIL, %g2
+	sethi	%hi(CC_ICLR), %o0
+	sethi	%hi(1 << 14), %o1
+	or	%o0, %lo(CC_ICLR), %o0
+	stha	%o1, [%o0] ASI_M_MXCC	/* Clear PIL 14 in MXCC's ICLR */
+	wr	%g2, 0x0, %psr
+	WRITE_PAUSE
+	wr	%g2, PSR_ET, %psr
+	WRITE_PAUSE
+	call	smp4d_percpu_timer_interrupt
+	 add	%sp, STACKFRAME_SZ, %o0
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+	RESTORE_ALL
+
+	.align	4
+	.globl	linux_trap_ipi15_sun4d
+linux_trap_ipi15_sun4d:
+	SAVE_ALL
+	sethi	%hi(CC_BASE), %o4
+	sethi	%hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2
+	or	%o4, (CC_EREG - CC_BASE), %o0
+	ldda	[%o0] ASI_M_MXCC, %o0
+	andcc	%o0, %o2, %g0
+	bne	1f
+	 sethi	%hi(BB_STAT2), %o2
+	lduba	[%o2] ASI_M_CTL, %o2
+	andcc	%o2, BB_STAT2_MASK, %g0
+	bne	2f
+	 or	%o4, (CC_ICLR - CC_BASE), %o0
+	sethi	%hi(1 << 15), %o1
+	stha	%o1, [%o0] ASI_M_MXCC	/* Clear PIL 15 in MXCC's ICLR */
+	or	%l0, PSR_PIL, %l4
+	wr	%l4, 0x0, %psr
+	WRITE_PAUSE
+	wr	%l4, PSR_ET, %psr
+	WRITE_PAUSE
+	call	smp4d_cross_call_irq
+	 nop
+	b	ret_trap_lockless_ipi
+	 clr	%l6
+
+1:	/* MXCC error */
+2:	/* BB error */
+	/* Disable PIL 15 */
+	set	CC_IMSK, %l4
+	lduha	[%l4] ASI_M_MXCC, %l5
+	sethi	%hi(1 << 15), %l7
+	or	%l5, %l7, %l5
+	stha	%l5, [%l4] ASI_M_MXCC
+	/* FIXME */
+1:	b,a	1b
+
+#endif /* CONFIG_SMP */
+
+	/* This routine handles illegal instructions and privileged
+	 * instruction attempts from user code.
+	 */
+	.align	4
+	.globl	bad_instruction
+bad_instruction:
+	sethi	%hi(0xc1f80000), %l4
+	ld	[%l1], %l5
+	sethi	%hi(0x81d80000), %l7
+	and	%l5, %l4, %l5
+	cmp	%l5, %l7
+	be	1f
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	do_illegal_instruction
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+1:	/* unimplemented flush - just skip */
+	jmpl	%l2, %g0
+	 rett	%l2 + 4
+
+	.align	4
+	.globl	priv_instruction
+priv_instruction:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	do_priv_instruction
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles unaligned data accesses. */
+	.align	4
+	.globl	mna_handler
+mna_handler:
+	andcc	%l0, PSR_PS, %g0
+	be	mna_fromuser
+	 nop
+
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	ld	[%l1], %o1
+	call	kernel_unaligned_trap
+	 add	%sp, STACKFRAME_SZ, %o0
+
+	RESTORE_ALL
+
+mna_fromuser:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	ld	[%l1], %o1
+	call	user_unaligned_trap
+	 add	%sp, STACKFRAME_SZ, %o0
+
+	RESTORE_ALL
+
+	/* This routine handles floating point disabled traps. */
+	.align	4
+	.globl	fpd_trap_handler
+fpd_trap_handler:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	do_fpd_trap
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Floating Point Exceptions. */
+	.align	4
+	.globl	fpe_trap_handler
+fpe_trap_handler:
+	set	fpsave_magic, %l5
+	cmp	%l1, %l5
+	be	1f
+	 sethi	%hi(fpsave), %l5
+	or	%l5, %lo(fpsave), %l5
+	cmp	%l1, %l5
+	bne	2f
+	 sethi	%hi(fpsave_catch2), %l5
+	or	%l5, %lo(fpsave_catch2), %l5
+	wr	%l0, 0x0, %psr
+	WRITE_PAUSE
+	jmp	%l5
+	 rett	%l5 + 4
+1:	
+	sethi	%hi(fpsave_catch), %l5
+	or	%l5, %lo(fpsave_catch), %l5
+	wr	%l0, 0x0, %psr
+	WRITE_PAUSE
+	jmp	%l5
+	 rett	%l5 + 4
+
+2:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	do_fpe_trap
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Tag Overflow Exceptions. */
+	.align	4
+	.globl	do_tag_overflow
+do_tag_overflow:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_tag_overflow
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Watchpoint Exceptions. */
+	.align	4
+	.globl	do_watchpoint
+do_watchpoint:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_watchpoint
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Register Access Exceptions. */
+	.align	4
+	.globl	do_reg_access
+do_reg_access:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_reg_access
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Co-Processor Disabled Exceptions. */
+	.align	4
+	.globl	do_cp_disabled
+do_cp_disabled:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_cp_disabled
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Co-Processor Exceptions. */
+	.align	4
+	.globl	do_cp_exception
+do_cp_exception:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_cp_exception
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	/* This routine handles Hardware Divide By Zero Exceptions. */
+	.align	4
+	.globl	do_hw_divzero
+do_hw_divzero:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr		! re-enable traps
+	WRITE_PAUSE
+
+	add	%sp, STACKFRAME_SZ, %o0
+	mov	%l1, %o1
+	mov	%l2, %o2
+	call	handle_hw_divzero
+	 mov	%l0, %o3
+
+	RESTORE_ALL
+
+	.align	4
+	.globl	do_flush_windows
+do_flush_windows:
+	SAVE_ALL
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	andcc	%l0, PSR_PS, %g0
+	bne	dfw_kernel
+	 nop
+
+	call	flush_user_windows
+	 nop
+
+	/* Advance over the trap instruction. */
+	ld	[%sp + STACKFRAME_SZ + PT_NPC], %l1
+	add	%l1, 0x4, %l2
+	st	%l1, [%sp + STACKFRAME_SZ + PT_PC]
+	st	%l2, [%sp + STACKFRAME_SZ + PT_NPC]
+
+	RESTORE_ALL
+
+	.globl	flush_patch_one
+
+	/* We get these for debugging routines using __builtin_return_address() */
+dfw_kernel:
+flush_patch_one:
+	FLUSH_ALL_KERNEL_WINDOWS
+
+	/* Advance over the trap instruction. */
+	ld	[%sp + STACKFRAME_SZ + PT_NPC], %l1
+	add	%l1, 0x4, %l2
+	st	%l1, [%sp + STACKFRAME_SZ + PT_PC]
+	st	%l2, [%sp + STACKFRAME_SZ + PT_NPC]
+
+	RESTORE_ALL
+
+	/* The getcc software trap.  The user wants the condition codes from
+	 * the %psr in register %g1.
+	 */
+
+	.align	4
+	.globl	getcc_trap_handler
+getcc_trap_handler:
+	srl	%l0, 20, %g1	! give user
+	and	%g1, 0xf, %g1	! only ICC bits in %psr
+	jmp	%l2		! advance over trap instruction
+	rett	%l2 + 0x4	! like this...
+
+	/* The setcc software trap.  The user has condition codes in %g1
+	 * that it would like placed in the %psr.  Be careful not to flip
+	 * any unintentional bits!
+	 */
+
+	.align	4
+	.globl	setcc_trap_handler
+setcc_trap_handler:
+	sll	%g1, 0x14, %l4
+	set	PSR_ICC, %l5
+	andn	%l0, %l5, %l0	! clear ICC bits in %psr
+	and	%l4, %l5, %l4	! clear non-ICC bits in user value
+	or	%l4, %l0, %l4	! or them in... mix mix mix
+
+	wr	%l4, 0x0, %psr	! set new %psr
+	WRITE_PAUSE		! TI scumbags...
+
+	jmp	%l2		! advance over trap instruction
+	rett	%l2 + 0x4	! like this...
+
+	.align	4
+	.globl	linux_trap_nmi_sun4c
+linux_trap_nmi_sun4c:
+	SAVE_ALL
+
+	/* Ugh, we need to clear the IRQ line.  This is now
+	 * a very sun4c specific trap handler...
+	 */
+	sethi	%hi(interrupt_enable), %l5
+	ld	[%l5 + %lo(interrupt_enable)], %l5
+	ldub	[%l5], %l6
+	andn	%l6, INTS_ENAB, %l6
+	stb	%l6, [%l5]
+
+	/* Now it is safe to re-enable traps without recursion. */
+	or	%l0, PSR_PIL, %l0
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	/* Now call the c-code with the pt_regs frame ptr and the
+	 * memory error registers as arguments.  The ordering chosen
+	 * here is due to unlatching semantics.
+	 */
+	sethi	%hi(AC_SYNC_ERR), %o0
+	add	%o0, 0x4, %o0
+	lda	[%o0] ASI_CONTROL, %o2	! sync vaddr
+	sub	%o0, 0x4, %o0
+	lda	[%o0] ASI_CONTROL, %o1	! sync error
+	add	%o0, 0xc, %o0
+	lda	[%o0] ASI_CONTROL, %o4	! async vaddr
+	sub	%o0, 0x4, %o0
+	lda	[%o0] ASI_CONTROL, %o3	! async error
+	call	sparc_lvl15_nmi
+	 add	%sp, STACKFRAME_SZ, %o0
+
+	RESTORE_ALL
+
+	.align	4
+	.globl	invalid_segment_patch1_ff
+	.globl	invalid_segment_patch2_ff
+invalid_segment_patch1_ff:	cmp	%l4, 0xff
+invalid_segment_patch2_ff:	mov	0xff, %l3
+
+	.align	4
+	.globl	invalid_segment_patch1_1ff
+	.globl	invalid_segment_patch2_1ff
+invalid_segment_patch1_1ff:	cmp	%l4, 0x1ff
+invalid_segment_patch2_1ff:	mov	0x1ff, %l3
+
+	.align	4
+	.globl	num_context_patch1_16, num_context_patch2_16
+num_context_patch1_16:		mov	0x10, %l7
+num_context_patch2_16:		mov	0x10, %l7
+
+	.align	4
+	.globl	vac_linesize_patch_32
+vac_linesize_patch_32:		subcc	%l7, 32, %l7
+
+	.align	4
+	.globl	vac_hwflush_patch1_on, vac_hwflush_patch2_on
+
+/*
+ * Ugly, but we cant use hardware flushing on the sun4 and we'd require
+ * two instructions (Anton)
+ */
+#ifdef CONFIG_SUN4
+vac_hwflush_patch1_on:		nop
+#else
+vac_hwflush_patch1_on:		addcc	%l7, -PAGE_SIZE, %l7
+#endif
+
+vac_hwflush_patch2_on:		sta	%g0, [%l3 + %l7] ASI_HWFLUSHSEG
+
+	.globl	invalid_segment_patch1, invalid_segment_patch2
+	.globl	num_context_patch1
+	.globl	vac_linesize_patch, vac_hwflush_patch1
+	.globl	vac_hwflush_patch2
+
+	.align	4
+	.globl	sun4c_fault
+
+! %l0 = %psr
+! %l1 = %pc
+! %l2 = %npc
+! %l3 = %wim
+! %l7 = 1 for textfault
+! We want error in %l5, vaddr in %l6
+sun4c_fault:
+#ifdef CONFIG_SUN4
+	sethi	%hi(sun4c_memerr_reg), %l4
+	ld	[%l4+%lo(sun4c_memerr_reg)], %l4  ! memerr ctrl reg addr
+	ld	[%l4], %l6		! memerr ctrl reg
+	ld	[%l4 + 4], %l5		! memerr vaddr reg
+	andcc	%l6, 0x80, %g0		! check for error type
+	st	%g0, [%l4 + 4]		! clear the error
+	be	0f			! normal error
+	 sethi	%hi(AC_BUS_ERROR), %l4	! bus err reg addr
+
+	call	prom_halt	! something weird happened
+					! what exactly did happen?
+					! what should we do here?
+
+0:	or	%l4, %lo(AC_BUS_ERROR), %l4	! bus err reg addr
+	lduba	[%l4] ASI_CONTROL, %l6	! bus err reg
+
+	cmp    %l7, 1			! text fault?
+	be	1f			! yes
+	 nop
+
+	ld     [%l1], %l4		! load instruction that caused fault
+	srl	%l4, 21, %l4
+	andcc	%l4, 1, %g0		! store instruction?
+
+	be	1f			! no
+	 sethi	%hi(SUN4C_SYNC_BADWRITE), %l4 ! yep
+					! %lo(SUN4C_SYNC_BADWRITE) = 0
+	or	%l4, %l6, %l6		! set write bit to emulate sun4c
+1:
+#else
+	sethi	%hi(AC_SYNC_ERR), %l4
+	add	%l4, 0x4, %l6			! AC_SYNC_VA in %l6
+	lda	[%l6] ASI_CONTROL, %l5		! Address
+	lda	[%l4] ASI_CONTROL, %l6		! Error, retained for a bit
+#endif
+
+	andn	%l5, 0xfff, %l5			! Encode all info into l7
+	srl	%l6, 14, %l4
+
+	and	%l4, 2, %l4
+	or	%l5, %l4, %l4
+
+	or	%l4, %l7, %l7			! l7 = [addr,write,txtfault]
+
+	andcc	%l0, PSR_PS, %g0
+	be	sun4c_fault_fromuser
+	 andcc	%l7, 1, %g0			! Text fault?
+
+	be	1f
+	 sethi	%hi(KERNBASE), %l4
+
+	mov	%l1, %l5			! PC
+
+1:
+	cmp	%l5, %l4
+	blu	sun4c_fault_fromuser
+	 sethi	%hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4
+
+	/* If the kernel references a bum kernel pointer, or a pte which
+	 * points to a non existant page in ram, we will run this code
+	 * _forever_ and lock up the machine!!!!! So we must check for
+	 * this condition, the AC_SYNC_ERR bits are what we must examine.
+	 * Also a parity error would make this happen as well.  So we just
+	 * check that we are in fact servicing a tlb miss and not some
+	 * other type of fault for the kernel.
+	 */
+	andcc	%l6, 0x80, %g0
+	be	sun4c_fault_fromuser
+	 and	%l5, %l4, %l5
+
+	/* Test for NULL pte_t * in vmalloc area. */
+	sethi   %hi(VMALLOC_START), %l4
+	cmp     %l5, %l4
+	blu,a   invalid_segment_patch1
+	 lduXa	[%l5] ASI_SEGMAP, %l4
+
+	sethi   %hi(swapper_pg_dir), %l4
+	srl     %l5, SUN4C_PGDIR_SHIFT, %l6
+	or      %l4, %lo(swapper_pg_dir), %l4
+	sll     %l6, 2, %l6
+	ld      [%l4 + %l6], %l4
+#ifdef CONFIG_SUN4
+	sethi	%hi(PAGE_MASK), %l6
+	andcc	%l4, %l6, %g0
+#else
+	andcc   %l4, PAGE_MASK, %g0
+#endif
+	be      sun4c_fault_fromuser
+	 lduXa  [%l5] ASI_SEGMAP, %l4
+
+invalid_segment_patch1:
+	cmp	%l4, 0x7f
+	bne	1f
+	 sethi	%hi(sun4c_kfree_ring), %l4
+	or	%l4, %lo(sun4c_kfree_ring), %l4
+	ld	[%l4 + 0x18], %l3
+	deccc	%l3			! do we have a free entry?
+	bcs,a	2f			! no, unmap one.
+	 sethi	%hi(sun4c_kernel_ring), %l4
+
+	st	%l3, [%l4 + 0x18]	! sun4c_kfree_ring.num_entries--
+
+	ld	[%l4 + 0x00], %l6	! entry = sun4c_kfree_ring.ringhd.next
+	st	%l5, [%l6 + 0x08]	! entry->vaddr = address
+
+	ld	[%l6 + 0x00], %l3	! next = entry->next
+	ld	[%l6 + 0x04], %l7	! entry->prev
+
+	st	%l7, [%l3 + 0x04]	! next->prev = entry->prev
+	st	%l3, [%l7 + 0x00]	! entry->prev->next = next
+
+	sethi	%hi(sun4c_kernel_ring), %l4
+	or	%l4, %lo(sun4c_kernel_ring), %l4
+					! head = &sun4c_kernel_ring.ringhd
+
+	ld	[%l4 + 0x00], %l7	! head->next
+
+	st	%l4, [%l6 + 0x04]	! entry->prev = head
+	st	%l7, [%l6 + 0x00]	! entry->next = head->next
+	st	%l6, [%l7 + 0x04]	! head->next->prev = entry
+
+	st	%l6, [%l4 + 0x00]	! head->next = entry
+
+	ld	[%l4 + 0x18], %l3
+	inc	%l3			! sun4c_kernel_ring.num_entries++
+	st	%l3, [%l4 + 0x18]
+	b	4f
+	 ld	[%l6 + 0x08], %l5
+
+2:
+	or	%l4, %lo(sun4c_kernel_ring), %l4
+					! head = &sun4c_kernel_ring.ringhd
+
+	ld	[%l4 + 0x04], %l6	! entry = head->prev
+
+	ld	[%l6 + 0x08], %l3	! tmp = entry->vaddr
+
+	! Flush segment from the cache.
+#ifdef CONFIG_SUN4
+	sethi	%hi((128 * 1024)), %l7
+#else
+	sethi	%hi((64 * 1024)), %l7
+#endif
+9:
+vac_hwflush_patch1:
+vac_linesize_patch:
+	subcc	%l7, 16, %l7
+	bne	9b
+vac_hwflush_patch2:
+	 sta	%g0, [%l3 + %l7] ASI_FLUSHSEG
+
+	st	%l5, [%l6 + 0x08]	! entry->vaddr = address
+
+	ld	[%l6 + 0x00], %l5	! next = entry->next
+	ld	[%l6 + 0x04], %l7	! entry->prev
+
+	st	%l7, [%l5 + 0x04]	! next->prev = entry->prev
+	st	%l5, [%l7 + 0x00]	! entry->prev->next = next
+	st	%l4, [%l6 + 0x04]	! entry->prev = head
+
+	ld	[%l4 + 0x00], %l7	! head->next
+
+	st	%l7, [%l6 + 0x00]	! entry->next = head->next
+	st	%l6, [%l7 + 0x04]	! head->next->prev = entry
+	st	%l6, [%l4 + 0x00]	! head->next = entry
+
+	mov	%l3, %l5		! address = tmp
+
+4:
+num_context_patch1:
+	mov	0x08, %l7
+
+	ld	[%l6 + 0x08], %l4
+	ldub	[%l6 + 0x0c], %l3
+	or	%l4, %l3, %l4		! encode new vaddr/pseg into l4
+
+	sethi	%hi(AC_CONTEXT), %l3
+	lduba	[%l3] ASI_CONTROL, %l6
+
+	/* Invalidate old mapping, instantiate new mapping,
+	 * for each context.  Registers l6/l7 are live across
+	 * this loop.
+	 */
+3:	deccc	%l7
+	sethi	%hi(AC_CONTEXT), %l3
+	stba	%l7, [%l3] ASI_CONTROL
+invalid_segment_patch2:
+	mov	0x7f, %l3
+	stXa	%l3, [%l5] ASI_SEGMAP
+	andn	%l4, 0x1ff, %l3
+	bne	3b
+	 stXa	%l4, [%l3] ASI_SEGMAP
+
+	sethi	%hi(AC_CONTEXT), %l3
+	stba	%l6, [%l3] ASI_CONTROL
+
+	andn	%l4, 0x1ff, %l5
+
+1:
+	sethi	%hi(VMALLOC_START), %l4
+	cmp	%l5, %l4
+
+	bgeu	1f
+	 mov	1 << (SUN4C_REAL_PGDIR_SHIFT - PAGE_SHIFT), %l7
+
+	sethi	%hi(KERNBASE), %l6
+
+	sub	%l5, %l6, %l4
+	srl	%l4, PAGE_SHIFT, %l4
+	sethi	%hi((SUN4C_PAGE_KERNEL & 0xf4000000)), %l3
+	or	%l3, %l4, %l3
+
+	sethi	%hi(PAGE_SIZE), %l4
+
+2:
+	sta	%l3, [%l5] ASI_PTE
+	deccc	%l7
+	inc	%l3
+	bne	2b
+	 add	%l5, %l4, %l5
+
+	b	7f
+	 sethi	%hi(sun4c_kernel_faults), %l4
+
+1:
+	srl	%l5, SUN4C_PGDIR_SHIFT, %l3
+	sethi	%hi(swapper_pg_dir), %l4
+	or	%l4, %lo(swapper_pg_dir), %l4
+	sll	%l3, 2, %l3
+	ld	[%l4 + %l3], %l4
+#ifndef CONFIG_SUN4
+	and	%l4, PAGE_MASK, %l4
+#else
+	sethi	%hi(PAGE_MASK), %l6
+	and	%l4, %l6, %l4
+#endif
+
+	srl	%l5, (PAGE_SHIFT - 2), %l6
+	and	%l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6
+	add	%l6, %l4, %l6
+
+	sethi	%hi(PAGE_SIZE), %l4
+
+2:
+	ld	[%l6], %l3
+	deccc	%l7
+	sta	%l3, [%l5] ASI_PTE
+	add	%l6, 0x4, %l6
+	bne	2b
+	 add	%l5, %l4, %l5
+
+	sethi	%hi(sun4c_kernel_faults), %l4
+7:
+	ld	[%l4 + %lo(sun4c_kernel_faults)], %l3
+	inc	%l3
+	st	%l3, [%l4 + %lo(sun4c_kernel_faults)]
+
+	/* Restore condition codes */
+	wr	%l0, 0x0, %psr
+	WRITE_PAUSE
+	jmp	%l1
+	 rett	%l2
+
+sun4c_fault_fromuser:
+	SAVE_ALL
+	 nop
+	
+	mov	%l7, %o1		! Decode the info from %l7
+	mov	%l7, %o2
+	and	%o1, 1, %o1		! arg2 = text_faultp
+	mov	%l7, %o3
+	and	%o2, 2, %o2		! arg3 = writep
+	andn	%o3, 0xfff, %o3		! arg4 = faulting address
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	call	do_sun4c_fault
+	 add	%sp, STACKFRAME_SZ, %o0	! arg1 = pt_regs ptr
+
+	RESTORE_ALL
+
+	.align	4
+	.globl	srmmu_fault
+srmmu_fault:
+	mov	0x400, %l5
+	mov	0x300, %l4
+
+	lda	[%l5] ASI_M_MMUREGS, %l6	! read sfar first
+	lda	[%l4] ASI_M_MMUREGS, %l5	! read sfsr last
+
+	andn	%l6, 0xfff, %l6
+	srl	%l5, 6, %l5			! and encode all info into l7
+
+	and	%l5, 2, %l5
+	or	%l5, %l6, %l6
+
+	or	%l6, %l7, %l7			! l7 = [addr,write,txtfault]
+
+	SAVE_ALL
+
+	mov	%l7, %o1
+	mov	%l7, %o2
+	and	%o1, 1, %o1		! arg2 = text_faultp
+	mov	%l7, %o3
+	and	%o2, 2, %o2		! arg3 = writep
+	andn	%o3, 0xfff, %o3		! arg4 = faulting address
+
+	wr	%l0, PSR_ET, %psr
+	WRITE_PAUSE
+
+	call	do_sparc_fault
+	 add	%sp, STACKFRAME_SZ, %o0	! arg1 = pt_regs ptr
+
+	RESTORE_ALL
+
+#ifdef CONFIG_SUNOS_EMUL
+	/* SunOS uses syscall zero as the 'indirect syscall' it looks
+	 * like indir_syscall(scall_num, arg0, arg1, arg2...);  etc.
+	 * This is complete brain damage.
+	 */
+	.globl	sunos_indir
+sunos_indir:
+	mov	%o7, %l4
+	cmp	%o0, NR_SYSCALLS
+	blu,a	1f
+	 sll	%o0, 0x2, %o0
+
+	sethi	%hi(sunos_nosys), %l6
+	b	2f
+	 or	%l6, %lo(sunos_nosys), %l6
+
+1:
+	set	sunos_sys_table, %l7
+	ld	[%l7 + %o0], %l6
+
+2:	
+	mov	%o1, %o0
+	mov	%o2, %o1
+	mov	%o3, %o2
+	mov	%o4, %o3
+	mov	%o5, %o4
+	call	%l6
+	 mov	%l4, %o7
+#endif
+
+	.align	4
+	.globl	sys_nis_syscall
+sys_nis_syscall:
+	mov	%o7, %l5
+	add	%sp, STACKFRAME_SZ, %o0		! pt_regs *regs arg
+	call	c_sys_nis_syscall
+	 mov	%l5, %o7
+
+	.align 4
+	.globl	sys_ptrace
+sys_ptrace:
+	call	do_ptrace
+	 add	%sp, STACKFRAME_SZ, %o0
+
+	ld	[%curptr + TI_FLAGS], %l5
+	andcc	%l5, _TIF_SYSCALL_TRACE, %g0
+	be	1f
+	 nop
+
+	call	syscall_trace
+	 nop
+
+1:
+	RESTORE_ALL
+
+	.align	4
+	.globl	sys_execve
+sys_execve:
+	mov	%o7, %l5
+	add	%sp, STACKFRAME_SZ, %o0		! pt_regs *regs arg
+	call	sparc_execve
+	 mov	%l5, %o7
+
+	.align	4
+	.globl	sys_pipe
+sys_pipe:
+	mov	%o7, %l5
+	add	%sp, STACKFRAME_SZ, %o0		! pt_regs *regs arg
+	call	sparc_pipe
+	 mov	%l5, %o7
+
+	.align	4
+	.globl	sys_sigaltstack
+sys_sigaltstack:
+	mov	%o7, %l5
+	mov	%fp, %o2
+	call	do_sigaltstack
+	 mov	%l5, %o7
+
+	.align	4
+	.globl	sys_sigstack
+sys_sigstack:
+	mov	%o7, %l5
+	mov	%fp, %o2
+	call	do_sys_sigstack
+	 mov	%l5, %o7
+
+	.align	4
+	.globl	sys_sigpause
+sys_sigpause:
+	/* Note: %o0 already has correct value... */
+	call	do_sigpause
+	 add	%sp, STACKFRAME_SZ, %o1
+
+	ld	[%curptr + TI_FLAGS], %l5
+	andcc	%l5, _TIF_SYSCALL_TRACE, %g0
+	be	1f
+	 nop
+
+	call	syscall_trace
+	 nop
+
+1:
+	/* We are returning to a signal handler. */
+	RESTORE_ALL
+
+	.align	4
+	.globl	sys_sigsuspend
+sys_sigsuspend:
+	call	do_sigsuspend
+	 add	%sp, STACKFRAME_SZ, %o0
+
+	ld	[%curptr + TI_FLAGS], %l5
+	andcc	%l5, _TIF_SYSCALL_TRACE, %g0
+	be	1f
+	 nop
+
+	call	syscall_trace
+	 nop
+
+1:
+	/* We are returning to a signal handler. */
+	RESTORE_ALL
+
+	.align	4
+	.globl	sys_rt_sigsuspend
+sys_rt_sigsuspend:
+	/* Note: %o0, %o1 already have correct value... */
+	call	do_rt_sigsuspend
+	 add	%sp, STACKFRAME_SZ, %o2
+
+	ld	[%curptr + TI_FLAGS], %l5
+	andcc	%l5, _TIF_SYSCALL_TRACE, %g0
+	be	1f
+	 nop
+
+	call	syscall_trace
+	 nop