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authorAndi Kleen <ak@suse.de>2005-10-30 01:49:38 -0500
committerChris Wright <chrisw@osdl.org>2005-11-24 14:10:11 -0800
commit067d66baa9df5b9e6bf7e442fc4ee7140ef3cc74 (patch)
tree7c76a89ee34901a3e4d37c93e399f751b30aee15 /arch/sparc/Makefile
parent4b490b0c8d0541d5857cb3f390607aa06ad876e7 (diff)
[PATCH] x86_64/i386: Compute correct MTRR mask on early Noconas
Force correct address space size for MTRR on some 64bit Intel Xeons They report 40bit, but only have 36bits of physical address space. This caused problems with setting up the correct masks for MTRR, resulting in incorrect MTRRs. CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86 and EM64T). Detail info can be found at: http://download.intel.com/design/Xeon/specupdt/30240216.pdf http://download.intel.com/design/Pentium4/specupdt/30235221.pdf Signed-off-by: Shaohua Li<shaohua.li@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Chris Wright <chrisw@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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