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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/sh/include
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/page.h2
-rw-r--r--arch/sh/include/asm/pgtable_32.h2
-rw-r--r--arch/sh/include/asm/unaligned-sh4a.h2
-rw-r--r--arch/sh/include/mach-common/mach/highlander.h4
-rw-r--r--arch/sh/include/mach-common/mach/r2d.h6
5 files changed, 8 insertions, 8 deletions
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index c4e0b3d472b..822d6084195 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -186,7 +186,7 @@ typedef struct page *pgtable_t;
/*
* While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
* happily generate {ld/st}.q pairs, requiring us to have 8-byte
- * alignment to avoid traps. The kmalloc alignment is gauranteed by
+ * alignment to avoid traps. The kmalloc alignment is guaranteed by
* virtue of L1_CACHE_BYTES, requiring this to only be special cased
* for slab caches.
*/
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index b799fe71114..0bce3d81569 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -167,7 +167,7 @@ static inline unsigned long copy_ptea_attributes(unsigned long x)
#endif
/*
- * Mask of bits that are to be preserved accross pgprot changes.
+ * Mask of bits that are to be preserved across pgprot changes.
*/
#define _PAGE_CHG_MASK \
(PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index c48a9c3420d..95adc500cab 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -9,7 +9,7 @@
* struct.
*
* The same note as with the movli.l/movco.l pair applies here, as long
- * as the load is gauranteed to be inlined, nothing else will hook in to
+ * as the load is guaranteed to be inlined, nothing else will hook in to
* r0 and we get the return value for free.
*
* NOTE: Due to the fact we require r0 encoding, care should be taken to
diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h
index 5d9d4d5154b..6ce944e33e5 100644
--- a/arch/sh/include/mach-common/mach/highlander.h
+++ b/arch/sh/include/mach-common/mach/highlander.h
@@ -24,7 +24,7 @@
#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
-#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
@@ -89,7 +89,7 @@
#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
-#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
diff --git a/arch/sh/include/mach-common/mach/r2d.h b/arch/sh/include/mach-common/mach/r2d.h
index 0a800157b82..e04f75eaa15 100644
--- a/arch/sh/include/mach-common/mach/r2d.h
+++ b/arch/sh/include/mach-common/mach/r2d.h
@@ -18,18 +18,18 @@
#define PA_DISPCTL 0xa4000008 /* Display Timing control */
#define PA_SDMPOW 0xa400000a /* SD Power control */
#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
-#define PA_PCICD 0xa400000e /* PCI Extention detect control */
+#define PA_PCICD 0xa400000e /* PCI Extension detect control */
#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
#define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
#define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
#define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */
-#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */
+#define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */
#define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
#define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */
#define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */
-#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */
+#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */
#define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
#define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */