sh: dma: More legacy cpu dma chainsawing.

Attempt to "tidy" up some of the multi IRQ handling and base + IRQ
management. This should keep it limping along without too much hassle,
and no new parts should ever be enabling or using this API anyways.

It doesn't get any closer to lipstick on a pig as this.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 0 insertions, 95 deletions

diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
deleted file mode 100644
index 9a4875a8963..00000000000
--- a/arch/sh/include/asm/dma-sh.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * arch/sh/include/asm/dma-sh.h
- *
- * Copyright (C) 2000  Takashi YOSHII
- * Copyright (C) 2003  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __DMA_SH_H
-#define __DMA_SH_H
-
-#include <asm/dma-register.h>
-#include <cpu/dma-register.h>
-#include <cpu/dma.h>
-
-/* DMAOR contorl: The DMAOR access size is different by CPU.*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
-    defined(CONFIG_CPU_SUBTYPE_SH7724)	|| \
-    defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
-    defined(CONFIG_CPU_SUBTYPE_SH7785)
-#define dmaor_read_reg(n) \
-    (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
-	: __raw_readw(SH_DMAC_BASE0 + DMAOR))
-#define dmaor_write_reg(n, data) \
-    (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
-    : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
-#else /* Other CPU */
-#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
-#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
-#endif
-
-static int dmte_irq_map[] __maybe_unused = {
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
-    DMTE0_IRQ,
-    DMTE0_IRQ + 1,
-    DMTE0_IRQ + 2,
-    DMTE0_IRQ + 3,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
-    DMTE4_IRQ,
-    DMTE4_IRQ + 1,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
-    DMTE6_IRQ,
-    DMTE6_IRQ + 1,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
-    DMTE8_IRQ,
-    DMTE9_IRQ,
-    DMTE10_IRQ,
-    DMTE11_IRQ,
-#endif
-};
-
-/*
- * Define the default configuration for dual address memory-memory transfer.
- * The 0x400 value represents auto-request, external->external.
- */
-#define RS_DUAL	(DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
-
-/* DMA base address */
-static u32 dma_base_addr[] __maybe_unused = {
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
-	SH_DMAC_BASE0 + 0x00,	/* channel 0 */
-	SH_DMAC_BASE0 + 0x10,
-	SH_DMAC_BASE0 + 0x20,
-	SH_DMAC_BASE0 + 0x30,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
-	SH_DMAC_BASE0 + 0x50,
-	SH_DMAC_BASE0 + 0x60,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
-	SH_DMAC_BASE1 + 0x00,
-	SH_DMAC_BASE1 + 0x10,
-#endif
-#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
-	SH_DMAC_BASE1 + 0x20,
-	SH_DMAC_BASE1 + 0x30,
-	SH_DMAC_BASE1 + 0x50,
-	SH_DMAC_BASE1 + 0x60, /* channel 11 */
-#endif
-};
-
-#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/cpu-sh4a/cpu/dma.h b/arch/sh/include/cpu-sh4a/cpu/dma.h
index c276313104c..89afb650ce2 100644
--- a/arch/sh/include/cpu-sh4a/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4a/cpu/dma.h
@@ -9,20 +9,17 @@
 #define DMTE4_IRQ	evt2irq(0xb80)
 #define DMAE0_IRQ	evt2irq(0xbc0)	/* DMA Error IRQ*/
 #define SH_DMAC_BASE0	0xFE008020
-#define SH_DMARS_BASE0	0xFE009000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 #define DMTE0_IRQ	evt2irq(0x800)
 #define DMTE4_IRQ	evt2irq(0xb80)
 #define DMAE0_IRQ	evt2irq(0xbc0)	/* DMA Error IRQ*/
 #define SH_DMAC_BASE0	0xFE008020
-#define SH_DMARS_BASE0	0xFE009000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 	defined(CONFIG_CPU_SUBTYPE_SH7764)
 #define DMTE0_IRQ	evt2irq(0x640)
 #define DMTE4_IRQ	evt2irq(0x780)
 #define DMAE0_IRQ	evt2irq(0x6c0)
 #define SH_DMAC_BASE0	0xFF608020
-#define SH_DMARS_BASE0	0xFF609000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 #define DMTE0_IRQ	evt2irq(0x800)	/* DMAC0A*/
 #define DMTE4_IRQ	evt2irq(0xb80)	/* DMAC0B */
@@ -35,7 +32,6 @@
 #define DMAE1_IRQ	evt2irq(0xb40)	/* DMA Error IRQ*/
 #define SH_DMAC_BASE0	0xFE008020
 #define SH_DMAC_BASE1	0xFDC08020
-#define SH_DMARS_BASE0	0xFDC09000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 #define DMTE0_IRQ	evt2irq(0x800)	/* DMAC0A*/
 #define DMTE4_IRQ	evt2irq(0xb80)	/* DMAC0B */
@@ -48,8 +44,6 @@
 #define DMAE1_IRQ	evt2irq(0xb40)	/* DMA Error IRQ*/
 #define SH_DMAC_BASE0	0xFE008020
 #define SH_DMAC_BASE1	0xFDC08020
-#define SH_DMARS_BASE0	0xFE009000
-#define SH_DMARS_BASE1	0xFDC09000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define DMTE0_IRQ	evt2irq(0x640)
 #define DMTE4_IRQ	evt2irq(0x780)
@@ -61,7 +55,6 @@
 #define DMAE0_IRQ	evt2irq(0x6c0)	/* DMA Error IRQ */
 #define SH_DMAC_BASE0	0xFC808020
 #define SH_DMAC_BASE1	0xFC818020
-#define SH_DMARS_BASE0	0xFC809000
 #else /* SH7785 */
 #define DMTE0_IRQ	evt2irq(0x620)
 #define DMTE4_IRQ	evt2irq(0x6a0)
@@ -74,7 +67,6 @@
 #define DMAE1_IRQ	evt2irq(0x940)	/* DMA Error IRQ1 */
 #define SH_DMAC_BASE0	0xFC808020
 #define SH_DMAC_BASE1	0xFCC08020
-#define SH_DMARS_BASE0	0xFC809000
 #endif
 
 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */