diff options
| author | Octavian Purdila <opurdila@ixiacom.com> | 2009-02-24 02:09:58 +0000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-11 17:10:16 +1100 |
| commit | f8ff96db9be035a01065a8528c016d125945479a (patch) | |
| tree | 101320f0691ddbf65722579c61b1dc99f19e2c73 /arch/powerpc/oprofile | |
| parent | 8f748aae4b5eda6a6ec3ab3554e7e19c7702ccc2 (diff) | |
powerpc/oprofile: G4 oprofile has variable number of counters
For ppc750 processors which use 4 performance counters instead of the
6 G4 uses but otherwise is compatible with G4.
Signed-off-by: Octavian Purdila <opurdila@ixiacom.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/oprofile')
| -rw-r--r-- | arch/powerpc/oprofile/op_model_7450.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/powerpc/oprofile/op_model_7450.c b/arch/powerpc/oprofile/op_model_7450.c index cc599eb8768..f8d36f940e8 100644 --- a/arch/powerpc/oprofile/op_model_7450.c +++ b/arch/powerpc/oprofile/op_model_7450.c @@ -29,7 +29,7 @@ static unsigned long reset_value[OP_MAX_COUNTER]; static int oprofile_running; -static u32 mmcr0_val, mmcr1_val, mmcr2_val; +static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs; #define MMCR0_PMC1_SHIFT 6 #define MMCR0_PMC2_SHIFT 0 @@ -88,13 +88,12 @@ static int fsl7450_cpu_setup(struct op_counter_config *ctr) mtspr(SPRN_MMCR0, mmcr0_val); mtspr(SPRN_MMCR1, mmcr1_val); - mtspr(SPRN_MMCR2, mmcr2_val); + if (num_pmcs > 4) + mtspr(SPRN_MMCR2, mmcr2_val); return 0; } -#define NUM_CTRS 6 - /* Configures the global settings for the countes on all CPUs. */ static int fsl7450_reg_setup(struct op_counter_config *ctr, struct op_system_config *sys, @@ -102,12 +101,13 @@ static int fsl7450_reg_setup(struct op_counter_config *ctr, { int i; + num_pmcs = num_ctrs; /* Our counters count up, and "count" refers to * how much before the next interrupt, and we interrupt * on overflow. So we calculate the starting value * which will give us "count" until overflow. * Then we set the events on the enabled counters */ - for (i = 0; i < NUM_CTRS; ++i) + for (i = 0; i < num_ctrs; ++i) reset_value[i] = 0x80000000UL - ctr[i].count; /* Set events for Counters 1 & 2 */ @@ -123,9 +123,10 @@ static int fsl7450_reg_setup(struct op_counter_config *ctr, /* Set events for Counters 3-6 */ mmcr1_val = mmcr1_event3(ctr[2].event) - | mmcr1_event4(ctr[3].event) - | mmcr1_event5(ctr[4].event) - | mmcr1_event6(ctr[5].event); + | mmcr1_event4(ctr[3].event); + if (num_ctrs > 4) + mmcr1_val |= mmcr1_event5(ctr[4].event) + | mmcr1_event6(ctr[5].event); mmcr2_val = 0; @@ -139,7 +140,7 @@ static int fsl7450_start(struct op_counter_config *ctr) mtmsr(mfmsr() | MSR_PMM); - for (i = 0; i < NUM_CTRS; ++i) { + for (i = 0; i < num_pmcs; ++i) { if (ctr[i].enabled) classic_ctr_write(i, reset_value[i]); else @@ -184,7 +185,7 @@ static void fsl7450_handle_interrupt(struct pt_regs *regs, pc = mfspr(SPRN_SIAR); is_kernel = is_kernel_addr(pc); - for (i = 0; i < NUM_CTRS; ++i) { + for (i = 0; i < num_pmcs; ++i) { val = classic_ctr_read(i); if (val < 0) { if (oprofile_running && ctr[i].enabled) { |