[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.

This patch converts the remaining 83xx boards to the dts-v1 format.
This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx,
mpc8349emitxgp and the mpc836x_mds.

The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already
dts-v1 and only undergo minor changes for the sake of formatting
consistency across the whole group of boards; i.e.  the idea being
that you can do a "diff -u board_A.dts board_B.dts" and see something
meaningful.

The general rule I've applied is that entries for values normally
parsed by humans are left in decimal (i.e. IRQ, cache size, clock
rates, basic counts and indexes) and all other data (i.e. reg and
ranges, IRQ flags etc.) remain in hex.

I've used dtc to confirm that the output prior to this changeset
matches the output after this changeset is applied for all boards.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 65 insertions, 65 deletions

diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 386f4a037b3..533e9b06cc8 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -31,11 +31,11 @@
 
 		PowerPC,8378@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <0x20>;
-			i-cache-line-size = <0x20>;
-			d-cache-size = <0x8000>;		// L1, 32K
-			i-cache-size = <0x8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <32768>;
+			i-cache-size = <32768>;
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -66,8 +66,8 @@
 			cell-index = <0>;
 			compatible = "fsl-i2c";
 			reg = <0x3000 0x100>;
-			interrupts = <0xe 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
 			dfsrr;
 		};
 
@@ -77,8 +77,8 @@
 			cell-index = <1>;
 			compatible = "fsl-i2c";
 			reg = <0x3100 0x100>;
-			interrupts = <0xf 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <15 0x8>;
+			interrupt-parent = <&ipic>;
 			dfsrr;
 		};
 
@@ -86,8 +86,8 @@
 			cell-index = <0>;
 			compatible = "fsl,spi";
 			reg = <0x7000 0x1000>;
-			interrupts = <0x10 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <16 0x8>;
+			interrupt-parent = <&ipic>;
 			mode = "cpu";
 		};
 
@@ -97,8 +97,8 @@
 			reg = <0x23000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupt-parent = < &ipic >;
-			interrupts = <0x26 0x8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <38 0x8>;
 			phy_type = "utmi_wide";
 		};
 
@@ -108,15 +108,15 @@
 			compatible = "fsl,gianfar-mdio";
 			reg = <0x24520 0x20>;
 			phy2: ethernet-phy@2 {
-				interrupt-parent = < &ipic >;
-				interrupts = <0x11 0x8>;
-				reg = <2>;
+				interrupt-parent = <&ipic>;
+				interrupts = <17 0x8>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 			phy3: ethernet-phy@3 {
-				interrupt-parent = < &ipic >;
-				interrupts = <0x12 0x8>;
-				reg = <3>;
+				interrupt-parent = <&ipic>;
+				interrupts = <18 0x8>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -128,10 +128,10 @@
 			compatible = "gianfar";
 			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
+			interrupts = <32 0x8 33 0x8 34 0x8>;
 			phy-connection-type = "mii";
-			interrupt-parent = < &ipic >;
-			phy-handle = < &phy2 >;
+			interrupt-parent = <&ipic>;
+			phy-handle = <&phy2>;
 		};
 
 		enet1: ethernet@25000 {
@@ -141,10 +141,10 @@
 			compatible = "gianfar";
 			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
+			interrupts = <35 0x8 36 0x8 37 0x8>;
 			phy-connection-type = "mii";
-			interrupt-parent = < &ipic >;
-			phy-handle = < &phy3 >;
+			interrupt-parent = <&ipic>;
+			phy-handle = <&phy3>;
 		};
 
 		serial0: serial@4500 {
@@ -153,8 +153,8 @@
 			compatible = "ns16550";
 			reg = <0x4500 0x100>;
 			clock-frequency = <0>;
-			interrupts = <0x9 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
 		};
 
 		serial1: serial@4600 {
@@ -163,19 +163,19 @@
 			compatible = "ns16550";
 			reg = <0x4600 0x100>;
 			clock-frequency = <0>;
-			interrupts = <0xa 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <10 0x8>;
+			interrupt-parent = <&ipic>;
 		};
 
 		crypto@30000 {
 			model = "SEC3";
 			compatible = "talitos";
 			reg = <0x30000 0x10000>;
-			interrupts = <0xb 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <11 0x8>;
+			interrupt-parent = <&ipic>;
 			/* Rev. 3.0 geometry */
 			num-channels = <4>;
-			channel-fifo-len = <0x18>;
+			channel-fifo-len = <24>;
 			exec-units-mask = <0x000001fe>;
 			descriptor-types-mask = <0x03ab0ebf>;
 		};
@@ -184,8 +184,8 @@
 			model = "eSDHC";
 			compatible = "fsl,esdhc";
 			reg = <0x2e000 0x1000>;
-			interrupts = <0x2a 0x8>;
-			interrupt-parent = < &ipic >;
+			interrupts = <42 0x8>;
+			interrupt-parent = <&ipic>;
 		};
 
 		/* IPIC
@@ -209,49 +209,49 @@
 		interrupt-map = <
 
 				/* IDSEL 0x11 */
-				 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
-				 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
-				 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
-				 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8
+				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
+				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
+				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
+				 0x8800 0x0 0x0 0x4 &ipic 23 0x8
 
 				/* IDSEL 0x12 */
-				 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8
-				 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8
-				 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8
-				 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8
+				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
+				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
+				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
+				 0x9000 0x0 0x0 0x4 &ipic 21 0x8
 
 				/* IDSEL 0x13 */
-				 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8
-				 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8
-				 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8
-				 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8
+				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
+				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
+				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
+				 0x9800 0x0 0x0 0x4 &ipic 22 0x8
 
 				/* IDSEL 0x15 */
-				 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8
-				 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8
-				 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8
-				 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8
+				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
+				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
+				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
+				 0xa800 0x0 0x0 0x4 &ipic 23 0x8
 
 				/* IDSEL 0x16 */
-				 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8
-				 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8
-				 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8
-				 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8
+				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
+				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
+				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
+				 0xb000 0x0 0x0 0x4 &ipic 22 0x8
 
 				/* IDSEL 0x17 */
-				 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8
-				 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8
-				 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8
-				 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8
+				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
+				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
+				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
+				 0xb800 0x0 0x0 0x4 &ipic 21 0x8
 
 				/* IDSEL 0x18 */
-				 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8
-				 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8
-				 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8
-				 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>;
-		interrupt-parent = < &ipic >;
-		interrupts = <0x42 0x8>;
-		bus-range = <0 0>;
+				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
+				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
+				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
+				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
+		interrupt-parent = <&ipic>;
+		interrupts = <66 0x8>;
+		bus-range = <0x0 0x0>;
 		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;