diff options
| author | Helge Deller <deller@parisc-linux.org> | 2006-04-20 20:40:23 +0000 |
|---|---|---|
| committer | Kyle McMartin <kyle@hera.kernel.org> | 2006-04-21 22:20:34 +0000 |
| commit | 2fd83038160531245099c3c5b3511fa4b80765eb (patch) | |
| tree | 6145a9e78723c76ceac722eb60267c0116983c12 /arch/parisc/kernel/entry.S | |
| parent | d668da80d613def981c573354e1853e38bd0698d (diff) | |
[PARISC] Further work for multiple page sizes
More work towards supporing multiple page sizes on 64-bit. Convert
some assumptions that 64bit uses 3 level page tables into testing
PT_NLEVELS. Also some BUG() to BUG_ON() conversions and some cleanups
to assembler.
Signed-off-by: Helge Deller <deller@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc/kernel/entry.S')
| -rw-r--r-- | arch/parisc/kernel/entry.S | 36 |
1 files changed, 22 insertions, 14 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 7c95d7663c2..d9e53cf0372 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -502,18 +502,20 @@ * all ILP32 processes and all the kernel for machines with * under 4GB of memory) */ .macro L3_ptep pgd,pte,index,va,fault +#if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */ extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index copy %r0,\pte - extrd,u,*= \va,31,32,%r0 + extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0 ldw,s \index(\pgd),\pgd - extrd,u,*= \va,31,32,%r0 + extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault - extrd,u,*= \va,31,32,%r0 + extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0 shld \pgd,PxD_VALUE_SHIFT,\index - extrd,u,*= \va,31,32,%r0 + extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0 copy \index,\pgd - extrd,u,*<> \va,31,32,%r0 + extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd +#endif L2_ptep \pgd,\pte,\index,\va,\fault .endm @@ -563,10 +565,18 @@ extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */ - /* Get rid of prot bits and convert to page addr for iitlbt and idtlbt */ + /* Enforce uncacheable pages. + * This should ONLY be use for MMIO on PA 2.0 machines. + * Memory/DMA is cache coherent on all PA2.0 machines we support + * (that means T-class is NOT supported) and the memory controllers + * on most of those machines only handles cache transactions. + */ + extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0 + depi 1,12,1,\prot - depd %r0,63,PAGE_SHIFT,\pte - extrd,s \pte,(63-PAGE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte + /* Drop prot bits and convert to page addr for iitlbt and idtlbt */ + extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte + depdi _PAGE_SIZE_ENCODING_DEFAULT,63,63-58,\pte .endm /* Identical macro to make_insert_tlb above, except it @@ -584,9 +594,8 @@ /* Get rid of prot bits and convert to page addr for iitlba */ - depi 0,31,PAGE_SHIFT,\pte + depi _PAGE_SIZE_ENCODING_DEFAULT,31,ASM_PFN_PTE_SHIFT,\pte extru \pte,24,25,\pte - .endm /* This is for ILP32 PA2.0 only. The TLB insertion needs @@ -1201,10 +1210,9 @@ intr_save: */ /* adjust isr/ior. */ - - extrd,u %r16,63,7,%r1 /* get high bits from isr for ior */ - depd %r1,31,7,%r17 /* deposit them into ior */ - depdi 0,63,7,%r16 /* clear them from isr */ + extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */ + depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */ + depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */ #endif STREG %r16, PT_ISR(%r29) STREG %r17, PT_IOR(%r29) |