diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2010-10-01 13:27:34 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 19:08:32 +0100 |
| commit | b93b2abce497873be97d765b848e0a955d29f200 (patch) | |
| tree | 0372a9162b8bbf67f5a5f7367a1da2001ea0292c /arch/mips/pci/pcie-octeon.c | |
| parent | ee71b7d2f834d5e4b3a43001b2fa88743ed71a2c (diff) | |
MIPS: Octeon: Rewrite DMA mapping functions.
All Octeon chips can support more than 4GB of RAM. Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.
Enable the swiotlb code to handle the cases where a device cannot directly
do DMA. This is a complete rewrite of the Octeon DMA mapping code.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/pcie-octeon.c')
| -rw-r--r-- | arch/mips/pci/pcie-octeon.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 861361e0c9a..385f035b24e 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -75,6 +75,8 @@ union cvmx_pcie_address { } mem; }; +#include <dma-coherence.h> + /** * Return the Core virtual base address for PCIe IO access. IOs are * read/written as an offset from this address. @@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void) cvmx_pcie_get_io_size(1) - 1; register_pci_controller(&octeon_pcie1_controller); } + + octeon_pci_dma_init(); + return 0; } |